| |
| 2001 | ||
|---|---|---|
| 1 | Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich: Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. ITC 2001: 461-469 | |
| 1 | Michael Kessler | [1] |
| 2 | Gundolf Kiefer | [1] |
| 3 | Jens Leenstra | [1] |
| 4 | Thomas Schwarz | [1] |
| 5 | Hans-Joachim Wunderlich | [1] |