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2001 | ||
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6 | William Eklow, Richard M. Sedmak, Dan Singletary, Toai Vo: Unsafe board states during PC-based boundary-scan testing. ITC 2001: 615-623 | |
1996 | ||
5 | EE | Richard M. Sedmak, John S. Evans: Spanning the Product Life Cycle: RASSP DFT. IEEE Design & Test of Computers 13(3): 32-42 (1996) |
1995 | ||
4 | Richard M. Sedmak, John Evans: A Hierarchical, Desgin-for-Testability (DFT) Methodology for the Rapid Prototyping of Application-Specific Signal Processors (RASSP). ITC 1995: 319-327 | |
1986 | ||
3 | Richard M. Sedmak: On the Possible Limits of External Testing. ITC 1986: 8 | |
1982 | ||
2 | Richard M. Sedmak: Self-Test Chip to System Level Approaches. ITC 1982: 182 | |
1980 | ||
1 | Richard M. Sedmak, Harris L. Liebergot: Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration. IEEE Trans. Computers 29(6): 492-500 (1980) |
1 | Bill Eklow (William Eklow) | [6] |
2 | John Evans | [4] |
3 | John S. Evans | [5] |
4 | Harris L. Liebergot | [1] |
5 | Dan Singletary | [6] |
6 | Toai Vo | [6] |