Vivek Chickermane

2005
17	EE	Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi: Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium 2005: 156-161
16	EE	Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman: Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium 2005: 470
2004
15	EE	Vivek Chickermane, Brian Foutz, Brion L. Keller: Channel Masking Synthesis for Efficient On-Chip Test Compression. ITC 2004: 452-461
14	EE	Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane: An Economic Analysis and ROI Model for Nanometer Test. ITC 2004: 518-524
2001
13		Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre: A building block BIST methodology for SOC designs: a case study. ITC 2001: 111-120
12	EE	Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane: System-on-Chip Testability Using LSSD Scan Structures. IEEE Design & Test of Computers 18(3): 83-97 (2001)
2000
11	EE	Vivek Chickermane, Scott Richter, Carl Barnhart: Integrating Logic BIST in VLSI Designs with Embedded Memories. VTS 2000: 157-164
1997
10		Vivek Chickermane, Kamran Zarrineh: Addressing Early Design-For-Test Synthesis in a Production Environment. ITC 1997: 246-255
1996
9	EE	Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer: A Design For Test Perspective on I/O Management. ICCD 1996: 46-
1995
8	EE	Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel: Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. VLSI Syst. 3(2): 333-338 (1995)
1994
7	EE	Vivek Chickermane, Jaushin Lee, Janak H. Patel: Addressing design for testability at the architectural level. IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 920-934 (1994)
6	EE	Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel: An observability enhancement approach for improved testability and at-speed test. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1051-1056 (1994)
1993
5	EE	Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel: Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC 1993: 236-241
1992
4	EE	Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel: APT: An Area-Performance-Testability Driven Placement Algorithm. DAC 1992: 141-146
3	EE	Vivek Chickermane, Jaushin Lee, Janak H. Patel: A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD 1992: 620-624
2		Vivek Chickermane, Jaushin Lee, Janak H. Patel: Design for Testability Using Architectural Descriptions. ITC 1992: 752-761
1991
1		Vivek Chickermane, Janak H. Patel: A Fault Oriented Partial Scan Design Approach. ICCAD 1991: 400-403

Coauthor Index

1	Prithviraj Banerjee (Prith Banerjee)	[4] [5] [8]
2	Carl Barnhart	[11]
3	Thomas Bartenstein	[14]
4	Brian Foutz	[15]
5	Patrick R. Gallagher Jr.	[13]
6	Steven Gregor	[13]
7	Brion L. Keller	[14] [15] [16] [17]
8	Sungho Kim	[4]
9	Jaushin Lee	[2] [3] [7]
10	Kevin McCauley	[16]
11	Hiroyuki Nakamura	[17]
12	Gareth Nicholls	[9]
13	Yoshihito Nishizaki	[17]
14	Mike Palmer	[9]
15	Janak H. Patel	[1] [2] [3] [4] [5] [6] [7] [8]
16	Thomas S. Pierre	[13]
17	Scott Richter	[11]
18	Elizabeth M. Rudnick	[5] [6] [8]
19	Akio Shirokane	[17]
20	Mick Tegethoff	[14]
21	Yoshihiko Terauchi	[17]
22	Tsutomu Ube	[17]
23	Shambhu J. Upadhyaya	[12]
24	Anis Uzzaman	[16] [17]
25	Kamran Zarrineh	[9] [10] [12]

Colors in the list of coauthors