| 2006 |
|---|
| 11 | EE | Jörg E. Vollrath,
Jürg Schwizer,
Marcin Gnat,
Ralf Schneider,
Bret Johnson:
DDR2 DRAM Output Timing Optimization.
MTDT 2006: 49-54 |
| 2005 |
|---|
| 10 | EE | Zaid Al-Ars,
Said Hamdioui,
Jörg E. Vollrath:
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach.
Asian Test Symposium 2005: 434-439 |
| 2003 |
|---|
| 9 | EE | Jörg E. Vollrath:
Output Timing Measurement Using an Idd Method.
MTDT 2003: 43-46 |
| 8 | EE | Jörg E. Vollrath:
Testing and Characterization of SDRAMs.
IEEE Design & Test of Computers 20(1): 42-50 (2003) |
| 2002 |
|---|
| 7 | EE | Jörg E. Vollrath:
Signal Margin Analysis for Memory Sense Amplifiers .
DELTA 2002: 123-127 |
| 2001 |
|---|
| 6 | | Jörg E. Vollrath,
Randall Rooney:
Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment.
ITC 2001: 768-775 |
| 5 | EE | Jörg E. Vollrath,
Ulf Lederer,
Thomas Hladschik:
Compressed Bit Fail Maps for Memory Fail Pattern Classification.
J. Electronic Testing 17(3-4): 291-297 (2001) |
| 2000 |
|---|
| 4 | EE | Jörg E. Vollrath:
Synchronous Dynamic Memory Test Construction: A Field Approach.
MTDT 2000: 59-64 |
| 1999 |
|---|
| 3 | EE | Jörg E. Vollrath:
Tutorial: Characterizing SDRAMS.
MTDT 1999: 62- |
| 1998 |
|---|
| 2 | EE | Jörg E. Vollrath,
Markus Huebl,
Ernst Stahl:
Power Analysis of DRAMs.
Asian Test Symposium 1998: 334-339 |
| 1997 |
|---|
| 1 | | Jörg E. Vollrath:
Cell Signal Measurement for High-Density DRAMs.
ITC 1997: 209-216 |
