Tsung-Chu Huang

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10EETsung-Chu Huang, Gau-Bin Chang, Ling Li: Congruence Synchronous Mirror Delay. ISCAS 2007: 2184-2187
9EEKuen-Jong Lee, Tsung-Chu Huang: An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. J. Electronic Testing 18(6): 627-636 (2002)
8EETsung-Chu Huang, Kuen-Jong Lee: A Low-Power LFSR Architecture. Asian Test Symposium 2001: 470
7 Tsung-Chu Huang, Kuen-Jong Lee: A token scan architecture for low power testing. ITC 2001: 660-669
6EETsung-Chu Huang, Kuen-Jong Lee: Reduction of power consumption in scan-based circuits during testapplication by an input control technique. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 911-917 (2001)
5EEKuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen: Peak-power reduction for multiple-scan circuits during test application. Asian Test Symposium 2000: 453-458
4EETsung-Chu Huang, Kuen-Jong Lee: An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Asian Test Symposium 1999: 315-320
3EEKuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang: BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. ACM Trans. Design Autom. Electr. Syst. 4(2): 194-218 (1999)
2EETsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee: Built-in current sensor designs based on the bulk-driven technique. Asian Test Symposium 1997: 384-
1EEKuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai: Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Asian Test Symposium 1996: 100-

Coauthor Index

1Gau-Bin Chang [10]
2Jih-Jeen Chen [5]
3Min-Cheng Huang [2]
4Kuen-Jong Lee [1] [2] [3] [4] [5] [6] [7] [8] [9]
5Ling Li [10]
6Jing-Jou Tang [1] [3]
7Cheng-Liang Tsai [1]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)