| 2007 |
|---|
| 10 | EE | Tsung-Chu Huang,
Gau-Bin Chang,
Ling Li:
Congruence Synchronous Mirror Delay.
ISCAS 2007: 2184-2187 |
| 2002 |
|---|
| 9 | EE | Kuen-Jong Lee,
Tsung-Chu Huang:
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.
J. Electronic Testing 18(6): 627-636 (2002) |
| 2001 |
|---|
| 8 | EE | Tsung-Chu Huang,
Kuen-Jong Lee:
A Low-Power LFSR Architecture.
Asian Test Symposium 2001: 470 |
| 7 | | Tsung-Chu Huang,
Kuen-Jong Lee:
A token scan architecture for low power testing.
ITC 2001: 660-669 |
| 6 | EE | Tsung-Chu Huang,
Kuen-Jong Lee:
Reduction of power consumption in scan-based circuits during testapplication by an input control technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 911-917 (2001) |
| 2000 |
|---|
| 5 | EE | Kuen-Jong Lee,
Tsung-Chu Huang,
Jih-Jeen Chen:
Peak-power reduction for multiple-scan circuits during test application.
Asian Test Symposium 2000: 453-458 |
| 1999 |
|---|
| 4 | EE | Tsung-Chu Huang,
Kuen-Jong Lee:
An Input Control Technique for Power Reduction in Scan Circuits During Test Application.
Asian Test Symposium 1999: 315-320 |
| 3 | EE | Kuen-Jong Lee,
Jing-Jou Tang,
Tsung-Chu Huang:
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.
ACM Trans. Design Autom. Electr. Syst. 4(2): 194-218 (1999) |
| 1997 |
|---|
| 2 | EE | Tsung-Chu Huang,
Min-Cheng Huang,
Kuen-Jong Lee:
Built-in current sensor designs based on the bulk-driven technique.
Asian Test Symposium 1997: 384- |
| 1996 |
|---|
| 1 | EE | Kuen-Jong Lee,
Jing-Jou Tang,
Tsung-Chu Huang,
Cheng-Liang Tsai:
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.
Asian Test Symposium 1996: 100- |
