| 2004 |
|---|
| 14 | EE | Brion L. Keller,
Mick Tegethoff,
Thomas Bartenstein,
Vivek Chickermane:
An Economic Analysis and ROI Model for Nanometer Test.
ITC 2004: 518-524 |
| 2001 |
|---|
| 13 | | Ajay Khoche,
Rohit Kapur,
David Armstrong,
Thomas W. Williams,
Mick Tegethoff,
Jochen Rivoir:
A new methodology for improved tester utilization.
ITC 2001: 916-923 |
| 1999 |
|---|
| 12 | EE | Von-Kyoung Kim,
Tom Chen,
Mick Tegethoff:
Fault Coverage Estimation for Early Stage of VLSI Design.
Great Lakes Symposium on VLSI 1999: 105-108 |
| 1997 |
|---|
| 11 | | Von-Kyoung Kim,
Tom Chen,
Mick Tegethoff:
ASIC Manufacturing Test Cost Prediction at Early Design Stage.
ITC 1997: 356-361 |
| 10 | EE | Mick Tegethoff,
Tom Chen:
Simulation Techniques for the Manufacturing Test of MCMs.
J. Electronic Testing 10(1-2): 137-149 (1997) |
| 1996 |
|---|
| 9 | | Mick Tegethoff,
Kenneth P. Parker,
Ken Lee:
Opens Board Test Coverage: When is 99% Really 40%?
ITC 1996: 333-339 |
| 8 | | Von-Kyoung Kim,
Mick Tegethoff,
Tom Chen:
ASIC Yield Estimation at Early Design Cycle.
ITC 1996: 590-594 |
| 7 | | Felix Frayman,
Mick Tegethoff,
Brenton White:
Issues in Optimizing the Test Process - A Telecom Case Study.
ITC 1996: 800-808 |
| 6 | EE | Mick Tegethoff,
Tom Chen:
Sensitivity Analysis of Critical Parameters in Board Test.
IEEE Design & Test of Computers 13(1): 58-63 (1996) |
| 1995 |
|---|
| 5 | EE | Mick Tegethoff,
Kenneth P. Parker:
IEEE Std 1149.1: Where Are We? Where From Here?
IEEE Design & Test of Computers 12(2): 53-59 (1995) |
| 1994 |
|---|
| 4 | | Mick Tegethoff,
Tom Chen:
Defects, Fault Coverage, Yield and Cost in Board Manufacturing.
ITC 1994: 539-547 |
| 3 | | Mick Tegethoff,
Tom Chen:
Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs.
ITC 1994: 903-910 |
| 1993 |
|---|
| 2 | | Mick Tegethoff:
IEEE 1149.1: How to Justify Implementation.
ITC 1993: 265 |
| 1992 |
|---|
| 1 | | Mick Tegethoff,
T. E. Figal,
S. W. Hird:
Board Test DFT Model for Computer Products.
ITC 1992: 367-371 |
