Jing-Reng Huang

2007
16	EE	Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu: STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. VLSI Syst. 15(5): 541-545 (2007)
2004
15	EE	Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee: An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222
14	EE	Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang: A Built-In Parametric Timing Measurement Unit. IEEE Design & Test of Computers 21(4): 322-330 (2004)
2002
13	EE	Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356-
12	EE	Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411-
11	EE	Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang: Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. DFT 2002: 117-128
2001
10	EE	Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu: Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium 2001: 91-96
9	EE	Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A low-cost CMOS time interval measurement core. ISCAS (4) 2001: 190-193
8		Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A built-in timing parametric measurement unit. ITC 2001: 315-322
7	EE	Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng: A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. VTS 2001: 198-203
6	EE	Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng: Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. VTS 2001: 204-209
2000
5	EE	Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu: A programmable built-in self-test core for embedded memories. ASP-DAC 2000: 11-12
4	EE	Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang: A realistic fault model for flash memories. Asian Test Symposium 2000: 274-281
3	EE	Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu: An FPGA-based re-configurable functional tester for memory chips. Asian Test Symposium 2000: 51-57
2	EE	Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai: BRAINS: A BIST Compiler for Embedded Memories. DFT 2000: 299-
1999
1	EE	Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang: A Programmable BIST Core for Embedded DRAM. IEEE Design & Test of Computers 16(1): 59-70 (1999)

Coauthor Index

1	Tsin-Yuan Chang	[1] [4] [8] [9] [14]
2	Chuang Cheng	[2]
3	Kuo-Liang Cheng	[10] [12] [13] [15] [16]
4	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[3] [6] [7]
5	Li-Ming Denq	[15]
6	Yea-Ling Horng	[4]
7	Ming-Jun Hsiao	[8] [9] [14]
8	Huan-Shan Hsu	[12]
9	Chia-Ming Hsueh	[10]
10	Chih-Tsun Huang	[1] [2] [5] [10] [12] [13] [15]
11	Shi-Yu Huang	[11]
12	Shin-Wei Hung	[15]
13	Madhu K. Iyer	[7]
14	Wei-Cheng Lai	[6]
15	Jye-Yuan Lee	[15]
16	Yen-Fu Lin	[13]
17	Youn-Long Lin	[12] [13]
18	Chih-Yen Lo	[15] [16]
19	Chee-Kian Ong	[3]
20	Ming-Chang Tsai	[2]
21	Chen-Hsing Wang	[16]
22	Chih-Wea Wang	[12] [13] [15] [16]
23	Horng-Bin Wang	[11]
24	Shin-Moe Wang	[16]
25	Chen-Jong Wey	[2]
26	Cheng-Wen Wu	[1] [2] [3] [5] [10] [12] [13] [16]
27	Chi-Feng Wu	[1]
28	Shao-Shen Yang	[8] [9]
29	Jen-Chieh Yeh	[10]