2008 |
36 | | Mohammad Tehranipoor,
Jim Plusquellic:
IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2008, Anaheim, CA, USA, June 9, 2008. Proceedings
IEEE Computer Society 2008 |
35 | EE | Xiaoxiao Wang,
Hassan Salmani,
Mohammad Tehranipoor,
James F. Plusquellic:
Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis.
DFT 2008: 87-95 |
34 | EE | Xiaoxiao Wang,
Mohammad Tehranipoor,
Jim Plusquellic:
Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions.
HOST 2008: 15-19 |
33 | EE | Reza M. Rad,
Jim Plusquellic,
Mohammad Tehranipoor:
Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals.
HOST 2008: 3-7 |
32 | EE | Reza M. Rad,
Xiaoxiao Wang,
Mohammad Tehranipoor,
Jim Plusquellic:
Power supply signal calibration techniques for improving detection resolution to hardware Trojans.
ICCAD 2008: 632-639 |
2007 |
31 | EE | Jeremy Lee,
Mohammad Tehranipoor,
Chintan Patel,
Jim Plusquellic:
Securing Designs against Scan-Based Side-Channel Attacks.
IEEE Trans. Dependable Sec. Comput. 4(4): 325-336 (2007) |
2006 |
30 | EE | Jeremy Lee,
Mohammad Tehranipoor,
Jim Plusquellic:
A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks.
VTS 2006: 94-99 |
29 | EE | Jim Plusquellic,
Dhruva Acharyya,
Abhishek Singh,
Mohammad Tehranipoor,
Chintan Patel:
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method.
IEEE Design & Test of Computers 23(4): 278-293 (2006) |
28 | EE | Abhishek Singh,
Jim Plusquellic,
Dhananjay S. Phatak,
Chintan Patel:
Defect Simulation Methodology for iDDT Testing.
J. Electronic Testing 22(3): 255-272 (2006) |
2005 |
27 | EE | Jeremy Lee,
Mohammad Tehranipoor,
Chintan Patel,
Jim Plusquellic:
Securing Scan Design Using Lock and Key Technique.
DFT 2005: 51-62 |
26 | EE | Nisar Ahmed,
C. P. Ravikumar,
Mohammad Tehranipoor,
Jim Plusquellic:
At-Speed Transition Fault Testing With Low Speed Scan Enable.
VTS 2005: 42-47 |
25 | EE | Dhruva Acharyya,
Jim Plusquellic:
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements.
VTS 2005: 433-438 |
24 | EE | Chintan Patel,
Abhishek Singh,
Jim Plusquellic:
Defect Detection Using Quiescent Signal Analysis.
J. Electronic Testing 21(5): 463-483 (2005) |
23 | EE | Sanat Kamal Bahl,
James F. Plusquellic,
Joseph Thomas:
A Comparitive Study of W-cdma Cell Search Designs.
Journal of Circuits, Systems, and Computers 14(1): 129-136 (2005) |
2004 |
22 | EE | Abhishek Singh,
Chintan Patel,
Jim Plusquellic:
On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing.
ITC 2004: 262-270 |
21 | EE | Chintan Patel,
Abhishek Singh,
Jim Plusquellic:
Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement.
ITC 2004: 319-328 |
20 | EE | Abhishek Singh,
Chintan Patel,
Jim Plusquellic:
Fault Simulation Model for i{DDT} Testing: An Investigation.
VTS 2004: 304-312 |
2003 |
19 | EE | Abhishek Singh,
Dhananjay S. Phatak,
Tom Goff,
Mike Riggs,
James F. Plusquellic,
Chintan Patel:
Comparison of Branching CORDIC Implementations.
ASAP 2003: 215-225 |
18 | EE | Sanat Kamal Bahl,
Jim Plusquellic:
FPGA implementation of a fast Hadamard transformer for WCDMA.
FPGA 2003: 237 |
17 | EE | Abhishek Singh,
Jitin Tharian,
Jim Plusquellic:
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis.
ICCAD 2003: 748-753 |
16 | EE | Dhruva Acharyya,
Jim Plusquellic:
Impedance Profile of a Commercial Power Grid and Test System.
ITC 2003: 709-718 |
15 | EE | Dhananjay S. Phatak,
Tom Goff,
Jim Plusquellic:
IP-in-IP tunneling to enable the simultaneous use of multiple IP interfaces for network level connection striping.
Computer Networks 43(6): 787-804 (2003) |
14 | EE | James F. Plusquellic,
Abhishek Singh,
Chintan Patel,
Anne E. Gattiker:
Power supply transient signal analysis for defect-oriented test.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 370-374 (2003) |
13 | EE | Chintan Patel,
Ernesto Staroswiecki,
Smita Pawar,
Dhruva Acharyya,
Jim Plusquellic:
Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids.
J. Electronic Testing 19(6): 611-623 (2003) |
2002 |
12 | EE | Abhishek Singh,
Jim Plusquellic,
Anne E. Gattiker:
Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models.
VTS 2002: 357-366 |
2001 |
11 | | Abhishek Singh,
Chintan Patel,
Shirong Liao,
James F. Plusquellic,
Anne E. Gattiker:
Detecting delay faults using power supply transient signal analysis.
ITC 2001: 395-404 |
10 | | Chintan Patel,
Fidel Muradali,
James F. Plusquellic:
Power supply transient signal integration circuit.
ITC 2001: 704-712 |
9 | EE | Chintan Patel,
Jim Plusquellic:
A Process and Technology-Tolerant IDDQ Method for IC Diagnosis.
VTS 2001: 145-152 |
8 | EE | Jim Plusquellic:
IC Diagnosis Using Multiple Supply Pad IDDQs.
IEEE Design & Test of Computers 18(1): 50-61 (2001) |
2000 |
7 | | James F. Plusquellic,
Amy Germida,
Jonathan Hudson,
Ernesto Staroswiecki,
Chintan Patel:
Predicting device performance from pass/fail transient signal analysis data.
ITC 2000: 1070-1079 |
6 | EE | Amy Germida,
James F. Plusquellic:
Detection of CMOS Defects under Variable Processing Conditions.
VTS 2000: 195-204 |
1999 |
5 | EE | James F. Plusquellic,
Amy Germida,
Zheng Yan:
8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects.
DFT 1999: 68-76 |
4 | | Amy Germida,
Zheng Yan,
James F. Plusquellic,
Fidel Muradali:
Defect detection using power supply transient signal analysis.
ITC 1999: 67-76 |
1998 |
3 | EE | James F. Plusquellic,
Donald M. Chiarulli,
Steven P. Levitan:
Characterization of CMOS Defects using Transient Signal Analysis.
DFT 1998: 93-101 |
1997 |
2 | | James F. Plusquellic,
Donald M. Chiarulli,
Steven P. Levitan:
Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data.
ITC 1997: 40-49 |
1996 |
1 | | James F. Plusquellic,
Donald M. Chiarulli,
Steven P. Levitan:
Digital Integrated Circuit Testing using Transient Signal Analysis.
ITC 1996: 481-490 |