Fernando M. Gonçalves

2005
22		Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves: A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. FPL 2005: 481-486
2003
21	EE	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. IOLTS 2003: 164-165
2002
20	EE	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. DFT 2002: 216-224
19	EE	José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura: DARP - A Digital Audio Reconfigurable Processor. FPL 2002: 556-566
18	EE	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. J. Electronic Testing 18(2): 179-187 (2002)
17	EE	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. J. Electronic Testing 18(3): 285-294 (2002)
2001
16	EE	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. IOLTW 2001: 197-201
15		Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. ITC 2001: 377-385
14	EE	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. J. Electronic Testing 17(3-4): 311-319 (2001)
1999
13	EE	Fernando M. Gonçalves, João Paulo Teixeira: Teaching Microelectronic-Based Integrated Systems Design and Test. MSE 1999: 65-66
12	EE	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. VTS 1999: 326-332
11	EE	Fernando M. Gonçalves, João Paulo Teixeira: Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems. J. Electronic Testing 15(1-2): 41-52 (1999)
1998
10	EE	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Defect-oriented test quality assessment using fault sampling and simulation. ITC 1998: 35-42
9	EE	Fernando M. Gonçalves, João Paulo Teixeira: Sampling Techniques of Non-Equally Probable Faults in VLSI System. VTS 1998: 283-288
1997
8	EE	Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. DFT 1997: 29-37
1996
7	EE	José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams: Defect level evaluation in an IC design environment. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1286-1293 (1996)
1994
6		José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams: Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC 1994: 436-442
5		M. Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. ITC 1994: 720-728
1992
4		M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Physical DFT for High Coverage of Realistic Faults. ITC 1992: 642-651
1991
3		José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira: IC Defects-Based Testability Analysis. ITC 1991: 500-509
2	EE	João Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves: A methodology for testability enhancement at layout level. J. Electronic Testing 1(4): 287-299 (1991)
1990
1	EE	João Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves, R. Crespo: A strategy for testability enhancement at layout level. EURO-DAC 1990: 413-417

Coauthor Index

1	C. F. Beltrá Almeida	[1] [2]
2	Nuno Barreiro	[19]
3	M. Calha	[5]
4	P. Casimiro	[4]
5	Francesco Corsi	[7]
6	R. Crespo	[1]
7	J. Gonçalves	[1] [2]
8	Victor Gonçalves	[22]
9	Cristoforo Marzocca	[7]
10	João Moura	[19]
11	Marcelino B. Santos	[4] [5] [10] [12] [14] [15] [16] [17] [18] [20] [21]
12	M. Saraiva	[4]
13	José T. de Sousa	[3] [4] [6] [7] [19] [22]
14	Isabel C. Teixeira	[1] [2] [4] [5] [8] [10] [12] [14] [15] [16] [17] [18] [20] [21]
15	João Paulo Teixeira	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [20] [21]
16	Thomas W. Williams	[6] [7]