DATE 1998:
Paris,
France
1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France.
IEEE Computer Society 1998 BibTeX
Design Optimization of Building Blocks
HW/SW Partitioning and Communication Synthesis
Asynchronous and Hybrid VHDL-Based Design
Data Path and FPGA Testing
- Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Scheduling and Module Assignment for Reducing Bist Resources.
66-73
Electronic Edition (link) BibTeX
- Laurence Tianruo Yang, Zebo Peng:
An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis.
74-81
Electronic Edition (link) BibTeX
- Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian:
RAM-Based FPGA's: A Test Approach for the Configurable Logic.
82-88
Electronic Edition (link) BibTeX
- Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi:
Novel Technique for Testing FPGAs.
89-
Electronic Edition (link) BibTeX
Design Methods for High Performance Applications
Scheduling in Embedded Systems
Advanced Techniques for VHDL Design
Novel BIST Approaches
Architectures for Image Processing
- Claus Schneider, Martin Kayss, Thomas Hollstein, Jürgen Deicke:
From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms.
186-190
Electronic Edition (link) BibTeX
- A. M. Rassau, T. C. B. Yu, H. Cheung, Stefan Lachowicz, Kamran Eshraghian, W. A. Crossland, T. D. Wilkinson:
Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications.
191-195
Electronic Edition (link) BibTeX
- Isidoro Urriza, José I. Artigas, José I. García-Nicolás, Luis A. Barragan, Denis Navarro:
VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform.
196-
Electronic Edition (link) BibTeX
Scheduling and Analysis of HW/SW
Extensions to VHDL
Error Detection and Design Validation
IP Based System-on-a-Chip Design
Design Reuse Methodologies
- Manfred Koegst, Dieter Garte, Peter Conradi, Michael G. Wahl:
A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits.
292-296
Electronic Edition (link) BibTeX
- Serafín Olcoz, Lorenzo Ayuda, Ivan Izaguirre, Olga Peñalba:
VHDL Teamwork, Organization Units and Workspace Management.
297-302
Electronic Edition (link) BibTeX
- Jörg Böttger, Karlheinz Agsteiner, Dieter Monjau, Sören Schulze:
An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse.
303-
Electronic Edition (link) BibTeX
Flat and Timing-Driven Processor Design
Reconfigurable Systems
Digital Simulation and Estimation
Synthesis of Reprogrammable and Reconfigurable Architectures
- Andreas Pyttel, Alexander Sedlmeier, Christian Veith:
PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems.
370-376
Electronic Edition (link) BibTeX
- Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
A Constraint Driven Approach to Loop Pipelining and Register Binding.
377-383
Electronic Edition (link) BibTeX
- Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung:
Multiple Behavior Module Synthesis Based on Selective Groupings.
384-388
Electronic Edition (link) BibTeX
- Meenakshi Kaul, Ranga Vemuri:
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures.
389-
Electronic Edition (link) BibTeX
Partitioning and Routing
Panel - Formal Verification:
A New Standard CAD Tool for the Industrial Design Flow
Simulation for High-Level Design
Architectural Synthesis
Timing and Crosstalk in Interconnect
Panel:
Next Generation System Design Tools
IDDQ and Memory Testing
Microsystems
Interconnect Modeling
Design for Manufacturability - Embedded Tutorial
Sequential Circuit Testing
Issues in Behavioral Synthesis
Formal Equivalence Checking Using Decision Diagrams
Silicon Debug of Systems-on-Chips
Characterization and Verification of Analogue Circuits
Benchmark Circuits,
Technology Mapping and Scan Chains
Physical to Gate Level Design for Low-Power
Embedded Memory and Embedded Logic
Analogue Circuit Modeling and Design Methodology
Combinational Logical Synthesis
High Level Power Estimation
Petri Nets and Dedicated Formalisms
Mixed-Signal Test and DFT
Sequential Logic Synthesis
High-Level Power Optimization
System Architecture Design
Simulation and Test Tools for Analogue Circuits
Poster Session
- R. Niemann, Peter Marwedel:
Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems.
912-913
Electronic Edition (link) BibTeX
- Marisa Luisa López-Vallejo, Carlos Angel Iglesias, Juan Carlos López:
A Knowledge-based System for Hardware-Software Partitioning.
914-915
Electronic Edition (link) BibTeX
- Tom J. Kazmierski:
A Formal Description of VHDL-AMS Analogue Systems.
916-920
Electronic Edition (link) BibTeX
- Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe:
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique.
921-922
Electronic Edition (link) BibTeX
- Davor Runje, Mario Kovac:
Universal Strong Encryption FPGA Core Implementation.
923-924
Electronic Edition (link) BibTeX
- Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Data Cache Sizing for Embedded Processor Applications.
925-926
Electronic Edition (link) BibTeX
- Jean Paul Calvez, Dominique Heller, F. Muller, Olivier Pasquier:
A Programmable Multi-Language Generator for CoDesign.
927-928
Electronic Edition (link) BibTeX
- Anupam Basu, Rainer Leupers, Peter Marwedel:
Register-Constrained Address Computation in DSP Programs.
929-930
Electronic Edition (link) BibTeX
- Thomas Müller-Wipperfürth, Richard Hagelauer:
Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base.
931-932
Electronic Edition (link) BibTeX
- George Economakos, George K. Papakonstantinou, Panayotis Tsanakas:
AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems.
933-934
Electronic Edition (link) BibTeX
- Serafín Olcoz, Ana Castellvi, Maria Garcia, Jose Angel Gomez:
Static Analysis Tools for Soft-Core Reviews and Audits.
935-936
Electronic Edition (link) BibTeX
- Michael G. Wahl, Holger Völkel:
A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor.
937-938
Electronic Edition (link) BibTeX
- Hans-Georg Martin, Wolfgang Rosenstiel:
A Comparing Study of Technology Mapping for FPGA.
939-940
Electronic Edition (link) BibTeX
- Tom J. Kazmierski:
Fuzzy-logic digital-analogue interfaces for accurate mixed-signal simulation.
941-944
Electronic Edition (link) BibTeX
- Wonyong Sung, Soonhoi Ha:
Optimized Timed Hardware Software Cosimulation without Roll-back.
945-946
Electronic Edition (link) BibTeX
- Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez:
A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design.
947-948
Electronic Edition (link) BibTeX
- Jie Gong, Chih-Tung Chen, Kayhan Küçükçakar:
Architectural Rule Checking for High-level Synthesis.
949-950
Electronic Edition (link) BibTeX
- Hideaki Kimura, Norihito Iyenaga:
A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator.
951-952
Electronic Edition (link) BibTeX
- Petra Nordholz, Hartmut Grabinski, Dieter Treytnar, Jan Otterstedt, Dirk Niggemeyer, Uwe Arz, T. W. Williams:
Core Interconnect Testing Hazards.
953-954
Electronic Edition (link) BibTeX
- Teresa Riesgo, Yago Torroja, Eduardo de la Torre, J. Uceda:
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models.
955-956
Electronic Edition (link) BibTeX
- Cristiana Bolchini, Fabio Salice, Donatella Sciuto:
Fault Analysis in Networks with Concurrent Error Detection Properties.
957-958
Electronic Edition (link) BibTeX
- M. Svajda, B. Straka, Hans A. R. Manhaeve:
IOCIMU - An Integrated Off-Chip IDDQ Measurement Unit.
959-960
Electronic Edition (link) BibTeX
- Markus Wolf, Ulrich Kleine:
Automatic Topology Optimization for Analog Module Generators.
961-962
Electronic Edition (link) BibTeX
- Anatoly Prihozhy:
Asynchronous Scheduling and Allocation.
963-964
Electronic Edition (link) BibTeX
- Matthias Ringe, Thomas Lindenkreuz, Erich Barke:
Path Verification Using Boolean Satisfiability.
965-966
Electronic Edition (link) BibTeX
- Sumit Roy, Harm Arts, Prithviraj Banerjee:
PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions.
967-968
Electronic Edition (link) BibTeX
- Wolfgang Roethig, A. M. Zarkesh, M. Andrews:
Power and Timing Modeling for ASIC Designs.
969-970
Electronic Edition (link) BibTeX
- Bogdan G. Arsintescu, Ralph H. J. M. Otten:
Constraints Space Management for the Layout of Analog IC's.
971-972
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
A Synthesis Procedure for Flexible Logic Functions.
973-974
Electronic Edition (link) BibTeX
- Felix Nicoli:
Denotational Semantics of a Behavioral Subset of VHDL.
975-976
Electronic Edition (link) BibTeX
- José M. Mendías, Román Hermida:
Correct High-Level Synthesis: a Formal Perspective.
977-978
Electronic Edition (link) BibTeX
- Mehrdad Nourani, Christos A. Papachristou:
A Bypass Scheme for Core-Based System Fault Testing.
979-980
Electronic Edition (link) BibTeX
- Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly Testable and Compact 1-out-of-n Code Checker with Single Output.
981-982
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines.
983-984
Electronic Edition (link) BibTeX
- Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija:
CMOS Combinational Circuit Sizing by Stage-wise Tapering.
985-988
Electronic Edition (link) BibTeX
- Jaime Velasco-Medina, Th. Calin, Michael Nicolaidis:
Fault Detection for Linear Analog Circuits Using Current Injection.
987-
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:05:46 2009
by Michael Ley (ley@uni-trier.de)