Tohru Ishihara

2008
31	EE	Maziar Goudarzi, Tohru Ishihara: Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. ACM Great Lakes Symposium on VLSI 2008: 383-386
30	EE	Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura: Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI 2008: 403-406
29	EE	Maziar Goudarzi, Tohru Ishihara, Hamid Noori: Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. HiPEAC 2008: 224-239
28	EE	Maziar Goudarzi, Tohru Ishihara: Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. ISLPED 2008: 93-98
27	EE	Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara: Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. ISVLSI 2008: 447-450
26	EE	Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura: Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS 2008: 62-71
25	EE	Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato: AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP 2008: 83-88
24	EE	Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Transactions 91-C(4): 410-417 (2008)
2007
23	EE	Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura: A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC 2007: 878-883
22	EE	Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Task scheduling for reliable cache architectures of multiprocessor systems. DATE 2007: 1490-1495
21	EE	Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura: Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTImedia 2007: 13-18
20	EE	Tohru Ishihara, Farzan Fallah: A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors CoRR abs/0710.4703: (2007)
19	EE	Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Transactions 90-C(10): 1983-1991 (2007)
2006
18	EE	Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah: An Energy Characterization Framework for Software-Based Embedded Systems. ESTImedia 2006: 59-64
17	EE	Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto: A Simulation-Based Soft Error Estimation Methodology for Computer Systems. ISQED 2006: 196-203
2005
16	EE	Tohru Ishihara, Farzan Fallah: A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. DATE 2005: 358-363
15		Tohru Ishihara, Farzan Fallah: A cache-defect-aware code placement algorithm for improving the performance of processors. ICCAD 2005: 995-1001
14	EE	Tohru Ishihara, Farzan Fallah: A non-uniform cache architecture for low power system design. ISLPED 2005: 363-368
2003
13	EE	Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada: Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42
2002
12	EE	Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura: A Power Minimization Technique for Arithmetic Circuits by Cell Selection. VLSI Design 2002: 268-273
11	EE	Tohru Ishihara, Kunihiro Asada: An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. VLSI Design 2002: 282-287
2001
10	EE	Tohru Ishihara, Kunihiro Asada: A system level memory power optimization technique using multiple supply and threshold voltages. ASP-DAC 2001: 456-461
9	EE	Takanori Okuma, Hiroto Yasuura, Tohru Ishihara: Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Design & Test of Computers 18(2): 31-41 (2001)
2000
8	EE	Tohru Ishihara, Hiroto Yasuura: A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE 2000: 617-616
1999
7	EE	Koji Inoue, Tohru Ishihara, Kazuaki Murakami: Way-predicting set-associative cache for high performance and low energy consumption. ISLPED 1999: 273-275
6	EE	Takanori Okuma, Tohru Ishihara, Hiroto Yasuura: Real-Time Task Scheduling for a Variable Voltage Processor. ISSS 1999: 24-29
1998
5		Tohru Ishihara, Hiroto Yasuura: Power-Pro: Programmable Power Management Architecture. ASP-DAC 1998: 321-322
4	EE	Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura: Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860
3	EE	Tohru Ishihara, Hiroto Yasuura: Voltage scheduling problem for dynamically variable voltage processors. ISLPED 1998: 197-202
1996
2	EE	Tohru Ishihara, Hiroto Yasuura: Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED 1996: 117-120
1993
1		Tohru Ishihara, Masakazu Kojima: On the big Mu in the affine scaling algorithm. Math. Program. 62: 85-93 (1993)

Coauthor Index

1	Kunihiro Asada	[10] [11] [13]
2	Farzan Fallah	[14] [15] [16] [18] [20]
3	Masahiro Fujita	[13]
4	Maziar Goudarzi	[23] [27] [28] [29] [31]
5	Koji Hashimoto	[17]
6	Akihiko Hyodo	[12]
7	Makoto Ikeda	[13]
8	Akihiko Inoue	[4]
9	Koji Inoue	[7]
10	Yuriko Ishitobi	[21] [25]
11	Yusuke Kaneda	[25]
12	Masakazu Kojima	[1]
13	Satoshi Komatsu	[13]
14	Yuji Kunitake	[25]
15	Donghoon Lee	[18]
16	Tadayuki Matsumura	[25] [27] [30]
17	Kazuaki Murakami	[7] [19] [22] [24]
18	Masanori Muroyama	[12] [17] [18] [25] [26]
19	Hamid Noori	[29]
20	Takanori Okuma	[6] [9]
21	Yuichiro Oyama	[25]
22	Toshinori Sato	[25]
23	Makoto Sugihara	[17] [19] [22] [24]
24	Hiroyuki Tomiyama	[4]
25	Seiichiro Yamaguchi	[25]
26	Hiroto Yasuura	[2] [3] [4] [5] [6] [8] [9] [12] [18] [21] [23] [26] [30]

Colors in the list of coauthors