| 2004 |
|---|
| 11 | EE | Hans T. Heineken,
Jitendra Khare:
Test Strategies For a 40Gbps Framer SoC.
ITC 2004: 758-763 |
| 2000 |
|---|
| 10 | EE | Jitendra Khare,
Hans T. Heineken,
M. d'Abreu:
Cost Trade-Offs in System On Chip Designs.
VLSI Design 2000: 178-184 |
| 9 | EE | Saghir A. Shaikh,
Jitendra Khare,
Hans T. Heineken:
Manufacturability and Testability Oriented Synthesis.
VLSI Design 2000: 185-191 |
| 8 | EE | Charles H. Ouyang,
Hans T. Heineken,
Jitendra Khare,
Saghir A. Shaikh,
M. d'Abreu:
Maximizing Wafer Productivity Through Layout Optimization.
VLSI Design 2000: 192-197 |
| 1998 |
|---|
| 7 | EE | Wojciech Maly,
Pranab K. Nag,
Hans T. Heineken,
Jitendra Khare:
Design-Manufacturing Interface: Part I - Vision.
DATE 1998: 550-556 |
| 6 | EE | Wojciech Maly,
Pranab K. Nag,
Charles H. Ouyang,
Hans T. Heineken,
Jitendra Khare,
P. Simon:
Design-Manufacturing Interface: Part II - Applications.
DATE 1998: 557-562 |
| 5 | EE | Hans T. Heineken,
Wojciech Maly:
Performance - Manufacturability Tradeoffs in IC Design.
DATE 1998: 563- |
| 1997 |
|---|
| 4 | EE | Hans T. Heineken,
Jitendra Khare,
Wojciech Maly,
Pranab K. Nag,
Charles H. Ouyang,
Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface.
DAC 1997: 321-326 |
| 3 | EE | Witold A. Pleskacz,
Wojciech Maly,
Hans T. Heineken:
Detection of Yield Trends.
DFT 1997: 62-68 |
| 1996 |
|---|
| 2 | EE | Hans T. Heineken,
Wojciech Maly:
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs.
ICCAD 1996: 368-373 |
| 1 | EE | Wojciech Maly,
Hans T. Heineken,
Jitendra Khare,
Pranab K. Nag:
Design for manufacturability in submicron domain.
ICCAD 1996: 690-697 |
