| |
| 1998 | ||
|---|---|---|
| 3 | EE | Aiguo Lu, Guenter Stenz, Frank M. Johannes: Technology Mapping for Minimizing Gate and Routing Area. DATE 1998: 664-669 |
| 1997 | ||
| 2 | Xiaochun Lin, Erik L. Dagless, Aiguo Lu: Technology mapping of LUT based FPGAs for delay optimisation. FPL 1997: 245-254 | |
| 1994 | ||
| 1 | Aiguo Lu, Jonathan Saul, Erik L. Dagless: Architecture Oriented Logic Optimization for Lookup Table Based FPGAs. ICCD 1994: 26-29 | |
| 1 | Erik L. Dagless | [1] [2] |
| 2 | Frank M. Johannes | [3] |
| 3 | Xiaochun Lin | [2] |
| 4 | Jonathan Saul | [1] |
| 5 | Guenter Stenz | [3] |