Hiroto Yasuura

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68EETadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura: Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI 2008: 403-406
67EEYasunobu Nohara, Sozo Inoue, Hiroto Yasuura: A Secure High-Speed Identification Scheme for RFID Using Bloom Filters. ARES 2008: 717-722
66 Mohammad Mesbah Uddin, Salahuddin Muhammad Salim Zabir, Yasunobu Nohara, Hiroto Yasuura: A Framework of Authentic Post-Issuance Program Modification for Multi-Application Smart Cards. ICWN 2008: 288-294
65EEMasanori Muroyama, Tohru Ishihara, Hiroto Yasuura: Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS 2008: 62-71
64EEMohammad Mesbah Uddin, Yasunobu Nohara, Daisuke Ikeda, Hiroto Yasuura: A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification. IEICE Transactions 91-A(1): 229-235 (2008)
63EEMaziar Goudarzi, Tohru Ishihara, Hiroto Yasuura: A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC 2007: 878-883
62EEYuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura: Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTImedia 2007: 13-18
61EETomomi Yamasaki, Toru Nakamura, Kensuke Baba, Hiroto Yasuura: A Door Access Control System with Mobile Phones. PWC 2007: 230-240
60EEYasunobu Nohara, Sozo Inoue, Hiroto Yasuura: Unlinkability and Real World Constraints in RFID Systems. PerCom Workshops 2007: 371-376
59EESozo Inoue, Hiroto Yasuura, Daisuke Hagiwara: Systematic Error Detection for RFID Reliability. ARES 2006: 280-286
58EEDonghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah: An Energy Characterization Framework for Software-Based Embedded Systems. ESTImedia 2006: 59-64
57EETakahiro Watanabe, Yasunobu Nohara, Kensuke Baba, Sozo Inoue, Hiroto Yasuura: On Authentication between Human and Computer. PerCom Workshops 2006: 636-639
56EEMasanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura: A variation-aware low-power coding methodology for tightly coupled buses. ASP-DAC 2005: 557-560
55EEYasunobu Nohara, Sozo Inoue, Hiroto Yasuura: Toward Unlinkable ID Management for Multi-Service Environments. PerCom Workshops 2005: 115-119
54EEYasunobu Nohara, Sozo Inoue, Kensuke Baba, Hiroto Yasuura: Quantitative evaluation of unlinkable ID matching schemes. WPES 2005: 55-60
53EEKosuke Tarumi, Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura: Bitwidth Optimization for Low Power Digital FIR Filter Design. IEICE Transactions 88-A(4): 869-875 (2005)
52EEHiroto Yasuura, Shoji Kawahito: Special Section on Papers Selected from AP-ASIC 2004. IEICE Transactions 88-C(8): 1704 (2005)
51EEHiroto Yasuura: Digitally Named World: Challenges for New Social Infrastructures. ISQED 2004: 323
50EEAtsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura: Routing methodology for minimizing 1nterconnect energy dissipation. ACM Great Lakes Symposium on VLSI 2003: 120-123
49EEHiroto Yasuura: Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. DSD 2003: 17-22
48EEMasanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura: A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. DSD 2003: 408-415
47EEAtsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura: Reduction of coupling effects by optimizing the 3-D configuration of the routing grid. IEEE Trans. VLSI Syst. 11(5): 951-954 (2003)
46EEShoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura: A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. DSD 2002: 210-217
45EETakeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura: Power analysis techniques for SoC with improved wiring models. ISLPED 2002: 259-262
44EEShoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura: A low-power digital matched filter for spread-spectrum systems. ISLPED 2002: 301-306
43EETakanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura: Reducing access energy of on-chip data memory considering active data bitwidth. ISLPED 2002: 88-91
42EEHiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys: Special Session: Security on SoC. ISSS 2002: 192-194
41EEHiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao: Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. ISSS 2002: 201-206
40EEHiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin: An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems. ISSS 2002: 32-37
39EEMasanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura: A Power Minimization Technique for Arithmetic Circuits by Cell Selection. VLSI Design 2002: 268-273
38EEMakoto Sugihara, Hiroto Yasuura: Optimization of Test Accesses with a Combined BIST and External Test Scheme. VLSI Design 2002: 683-688
37EEYun Cao, Hiroto Yasuura: A system-level energy minimization approach using datapath width optimization. ISLPED 2001: 231-236
36 Barry Shackleford, Greg Snider, Richard J. Carter, Etsuko Okushi, Mitsuhiro Yasuda, Katsuhiko Seo, Hiroto Yasuura: A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. Genetic Programming and Evolvable Machines 2(1): 33-60 (2001)
35EETakanori Okuma, Hiroto Yasuura, Tohru Ishihara: Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Design & Test of Computers 18(2): 31-41 (2001)
34EEMasaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura: One language or more?: how can we design an SoC at a system level? ASP-DAC 2000: 653-654
33EEMakoto Sugihara, Hiroto Yasuura, Hiroshi Date: Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. DATE 2000: 134-140
32EEKei Hirose, Hiroto Yasuura: A Bus Delay Reduction Technique Considering Crosstalk. DATE 2000: 441-445
31EETohru Ishihara, Hiroto Yasuura: A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE 2000: 617-616
30EEBarry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura: An FPGA-based genetic algorithm machine (poster abstract). FPGA 2000: 218
29EETakanori Okuma, Tohru Ishihara, Hiroto Yasuura: Real-Time Task Scheduling for a Variable Voltage Processor. ISSS 1999: 24-29
28 Hiroyuki Tomiyama, Hiroto Yasuura: Module Selection Using Manufacturing Information. ASP-DAC 1998: 275-281
27 Tohru Ishihara, Hiroto Yasuura: Power-Pro: Programmable Power Management Architecture. ASP-DAC 1998: 321-322
26EEHiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura: Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860
25EETohru Ishihara, Hiroto Yasuura: Voltage scheduling problem for dynamically variable voltage processors. ISLPED 1998: 197-202
24EETakanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura: Instruction Encoding Techniques for Area Minimization of Instruction ROM. ISSS 1998: 125-130
23EEHiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura: Statistical Performance-Driven Module Binding in High-Level Synthesis. ISSS 1998: 66-71
22EEMakoto Sugihara, Hiroshi Date, Hiroto Yasuura: A novel test methodology for core-based system LSIs and a testing time minimization problem. ITC 1998: 465-
21EEHiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar: Embedded System Design Using Soft-Core Processor and Valen-C. J. Inf. Sci. Eng. 14(3): 587-603 (1998)
20EEFumio Suzuki, Hisao Koizumi, M. Hiramine, K. Yamamoto, Hiroto Yasuura, K. Okino: A HW/SW co-design environment for multi-media equipments development using inverse problem. CODES 1997: 153-160
19EEBarry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura: Memory-CPU Size Optimization for Embedded System Designs. DAC 1997: 246-251
18EEHiroyuki Tomiyama, Hiroto Yasuura: Code placement techniques for cache miss rate reduction. ACM Trans. Design Autom. Electr. Syst. 2(4): 410-429 (1997)
17EETohru Ishihara, Hiroto Yasuura: Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED 1996: 117-120
16EEHiroyuki Tomiyama, Hiroto Yasuura: Size-Constrained Code Placement for Cache Miss Rate Reduction. ISSS 1996: 96-104
15 Tetsuya Yamada, Hiroto Yasuura: On the Computational Power of Binary Decision Diagram with Redundant Variables. Formal Methods in System Design 8(1): 65-89 (1996)
14EENikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura: Design Reuse: Fact or Fiction? (Panel). DAC 1994: 562
13EETakashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura: A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing 1993: 308-317
12 Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura: Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits 1992: 183-192
11EENagisa Ishiura, Hiroto Yasuura, Shuzo Yajima: NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. DAC 1990: 8-13
10 M. Ohmura, Hiroto Yasuura, Keikichi Tamaru: Extraction of Functional Information from Combinatorial Circuits. ICCAD 1990: 176-179
9 Hiroto Yasuura: Locally Computable Coding for Unary Operations. Concurrency: Theory, Language, And Architecture 1989: 312-323
8EEHiroto Yasuura, Nagisa Ishiura: Semantics of a Hardware Design Language for Japanese Standardization. DAC 1989: 836-839
7EENagisa Ishiura, Hiroto Yasuura, Shuzo Yajima: High-Speed Logic Simulation on Vector Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 305-321 (1987)
6 Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima: High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. IEEE Trans. Computers 34(9): 789-796 (1985)
5 Hiroto Yasuura: On Parallel Computational Complexity of Unification. FGCS 1984: 235-243
4 Hiroto Yasuura, Shuzo Yajima: Hardware Algorithms for VLSI Systems. VLSI Engineering 1984: 105-129
3 Shuzo Yajima, Hiroto Yasuura: Hardware Algorithms and Logic Design Automation. An Overview and Progress Report. RIMS Symposium on Software Science and Engineering 1982: 147-164
2 Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima: The Parallel Enumeration Sorting Scheme for VLSI. IEEE Trans. Computers 31(12): 1192-1201 (1982)
1 Hiroto Yasuura: Width and Depth of Combinational Logic Circuits. Inf. Process. Lett. 13(4/5): 191-194 (1981)

Coauthor Index

1David Agnew [14]
2Kensuke Baba [54] [57] [61]
3Karen Bartleson [34]
4Raul Camposano [14]
5Yun Cao [37] [40] [41] [43]
6Richard J. Carter [36]
7Hiroshi Date [22] [33]
8Antun Domic [14]
9Nikil D. Dutt (Nikil Dutt) [14]
10Eko Fajar [21] [24]
11Farzan Fallah [58]
12Peter Flake [34]
13Daniel Gajski (Daniel D. Gajski) [34]
14Catherine H. Gebotys [42]
15Shoji Goto [44] [46]
16Maziar Goudarzi [63]
17Daisuke Hagiwara [59]
18Yasoo Harada [44] [45] [46]
19Takashi Hashimoto [13]
20M. Hiramine [20]
21Tetsuo Hironaka [13]
22Kei Hirose [32]
23Akihiko Hyodo [39] [48] [53]
24Daisuke Ikeda [64]
25Masaharu Imai [34]
26Akihiko Inoue [21] [23] [24] [26]
27Sozo Inoue [54] [55] [57] [59] [60] [67]
28Tohru Ishihara [17] [25] [26] [27] [29] [31] [35] [39] [58] [62] [63] [65] [68]
29Yuriko Ishitobi [62]
30Nagisa Ishiura [7] [8] [11]
31Takashi Iwamoto [30]
32Shoji Kawahito [52]
33Hisao Koizumi [19] [20] [30]
34Donghoon Lee [58]
35Koji Makiyama [56]
36Tadayuki Matsumura [68]
37Yoshifumi Matsushita [44] [45] [46] [47] [50]
38Vasily G. Moshnyaga [12]
39Mamoru Mukuno [45]
40Kazuaki Murakami [13]
41Masanori Muroyama [39] [43] [48] [53] [56] [58] [65]
42Toru Nakamura [61]
43Yasunobu Nohara [54] [55] [57] [60] [64] [66] [67]
44M. Ohmura [10]
45K. Okino [20]
46Takanori Okuma [24] [29] [35] [41] [43] [48]
47Etsuko Okushi [19] [30] [36]
48Srivaths Ravi [42]
49Wolfgang Rosenstiel [34]
50Atsushi Sakai [47] [50]
51Takeshi Sakamoto [45]
52Steven Schulz [34]
53Katsuhiko Seo [30] [36]
54Barry Shackleford [19] [30] [36]
55Gary Smith [34]
56Greg Snider [36]
57Makoto Sugihara [22] [33] [38]
58Fumio Suzuki [20]
59Naofumi Takagi [2] [6] [42]
60Norihisa Takayama [44]
61Norihisa Takayarna [46]
62Keikichi Tamaru [10] [12]
63Kosuke Tarumi [53] [56]
64Hiroyuki Tomiyama [16] [18] [19] [21] [23] [24] [26] [28] [41]
65Michael Torla [42]
66Mohammad Mesbah Uddin [40] [64] [66]
67Takahiro Watanabe [57]
68Manfred Wiesel [14]
69Shuzo Yajima [2] [3] [4] [6] [7] [11]
70Takashi Yamada [44] [45] [46] [47] [50]
71Tetsuya Yamada [15]
72K. Yamamoto [20]
73Tomomi Yamasaki [61]
74Mitsuhiro Yasuda [19] [30] [36]
75Salahuddin Muhammad Salim Zabir [66]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)