| 2001 |
|---|
| 13 | | Matthias F. M. Stallmann,
Franc Brglez,
Debabrata Ghosh:
Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization.
ACM Journal of Experimental Algorithmics 6: 8 (2001) |
| 1999 |
|---|
| 12 | EE | Matthias F. M. Stallmann,
Franc Brglez,
Debabrata Ghosh:
Heuristics and Experimental Design for Bigraph Crossing Number Minimization.
ALENEX 1999: 74-93 |
| 11 | EE | Debabrata Ghosh,
Franc Brglez:
Equivalence classes of circuit mutants for experimental design.
ISCAS (6) 1999: 432-435 |
| 10 | EE | Matthias F. M. Stallmann,
Franc Brglez,
Debabrata Ghosh:
Evaluating iterative improvement heuristics for bigraph crossing minimization.
ISCAS (6) 1999: 444-447 |
| 1998 |
|---|
| 9 | EE | Debabrata Ghosh,
Nevin Kapur,
Franc Brglez,
Justin E. Harlow III:
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking.
DATE 1998: 656-663 |
| 1997 |
|---|
| 8 | EE | Nevin Kapur,
Debabrata Ghosh,
Franc Brglez:
Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions.
ISPD 1997: 136-143 |
| 1995 |
|---|
| 7 | EE | Debabrata Ghosh,
Soumitra Kumar Nandy:
Wave pipelined architecture folding: a method to achieve low power and low area.
VLSI Design 1995: 184- |
| 6 | EE | Debabrata Ghosh,
S. K. Nandy:
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology.
IEEE Trans. VLSI Syst. 3(1): 36-48 (1995) |
| 1994 |
|---|
| 5 | | Debabrata Ghosh,
S. K. Nandy,
K. Parthasarathy:
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor.
VLSI Design 1994: 77-82 |
| 4 | | Debabrata Ghosh,
Shamik Sural,
S. K. Nandy:
A 600MHz Half-Bit Level Pipelined Multiplier Macrocell.
VLSI Design 1994: 95-100 |
| 1993 |
|---|
| 3 | EE | Debabrata Ghosh,
S. K. Nandy,
P. Sadayappan,
K. Parthasarathy:
Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving.
DAC 1993: 303-307 |
| 2 | | Debabrata Ghosh,
S. K. Nandy:
A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology.
ICCD 1993: 198-201 |
| 1 | | Debabrata Ghosh,
S. K. Nandy,
K. Parthasarathy,
V. Visvanathan:
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs.
VLSI Design 1993: 341-346 |
