| 2004 |
|---|
| 8 | EE | Jing Zeng,
Magdy S. Abadir,
A. Kolhatkar,
G. Vandling,
Li-C. Wang,
Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
ITC 2004: 31-37 |
| 7 | EE | Jing Zeng,
Magdy S. Abadir,
G. Vandling,
Li-C. Wang,
S. Karako,
Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
MTV 2004: 103-109 |
| 2003 |
|---|
| 6 | EE | Magdy S. Abadir,
Jing Zeng,
Carol Pyron,
Juhong Zhu:
Automated Test Model Generation from Switch Level Custom Circuits.
Asian Test Symposium 2003: 184-189 |
| 2002 |
|---|
| 5 | EE | Jing Zeng,
Magdy S. Abadir,
Jacob A. Abraham:
False timing path identification using ATPG techniques and delay-based information.
DAC 2002: 562-565 |
| 2001 |
|---|
| 4 | EE | Jing Zeng,
Magdy S. Abadir,
Jayanta Bhadra,
Jacob A. Abraham:
Full chip false timing path identification: applications to the PowerPCTM microprocessors.
DATE 2001: 514-519 |
| 1998 |
|---|
| 3 | EE | Li-C. Wang,
Magdy S. Abadir,
Jing Zeng:
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.
DATE 1998: 273-277 |
| 2 | EE | Li-C. Wang,
Magdy S. Abadir,
Jing Zeng:
On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays.
VTS 1998: 260-265 |
| 1 | EE | Li-C. Wang,
Magdy S. Abadir,
Jing Zeng:
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.
ACM Trans. Design Autom. Electr. Syst. 3(4): 524-532 (1998) |
