2009 | ||
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39 | EE | Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur: Evaluation of Analog/RF Test Measurements at the Design Stage. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 582-590 (2009) |
2008 | ||
38 | EE | Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir: A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. DATE 2008: 68-73 |
2007 | ||
37 | EE | Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro: Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model. DATE 2007: 731-736 |
36 | EE | Emmanuel Simeu, Salvador Mir, R. Kherreddine, H. N. Nguyen: Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches. IOLTS 2007: 237-243 |
35 | EE | Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez: Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing. J. Electronic Testing 23(6): 471-484 (2007) |
2006 | ||
34 | EE | Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur: Pseudorandom functional BIST for linear and nonlinear MEMS. DATE 2006: 664-669 |
33 | EE | Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu: CAT platform for analogue and mixed-signal test evaluation and optimization. VLSI-SoC 2006: 320-325 |
32 | EE | Livier Lizzarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur: Study of a BIST Technique for CMOS Active Pixel Sensors. VLSI-SoC 2006: 326-331 |
31 | EE | Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro: A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters. VTS 2006: 314-319 |
30 | EE | Salvador Mir, Tim Cheng, Andrew Richardson: Guest Editorial. J. Electronic Testing 22(4-6): 311 (2006) |
29 | EE | Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro: A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting. J. Electronic Testing 22(4-6): 325-335 (2006) |
28 | EE | Salvador Mir, Libor Rufer, Achraf Dhayni: Built-in-self-test techniques for MEMS. Microelectronics Journal 37(12): 1591-1597 (2006) |
2005 | ||
27 | EE | Rabeb Kheriji, V. Danelon, Jean-Louis Carbonéro, Salvador Mir: Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach. DATE 2005: 170-171 |
26 | EE | Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur: On-chip Pseudorandom Testing for Linear and Nonlinear MEMS. VLSI-SoC 2005: 245-266 |
25 | EE | Libor Rufer, Salvador Mir, Emmanuel Simeu, C. Domingues: On-Chip Pseudorandom MEMS Testing. J. Electronic Testing 21(3): 233-241 (2005) |
24 | EE | Bozena Kaminska, Stephen K. Sunter, Salvador Mir: Analog and mixed signal test techniques for SOC development. Microelectronics Journal 36(12): 1063 (2005) |
23 | EE | Guillaume Prenat, Salvador Mir, Diego Vázquez, Luís Rolíndez: A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation. Microelectronics Journal 36(12): 1080-1090 (2005) |
2004 | ||
22 | EE | Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur: A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. DATE 2004: 706-707 |
21 | EE | Salvador Mir, Libor Rufer, Bernard Courtois: On-chip testing of embedded transducers. VLSI Design 2004: 463- |
2003 | ||
20 | EE | Mohammad A. Naal, Emmanuel Simeu, Salvador Mir: On-Line Testable Decimation Filter Design for AMS Systems. IOLTS 2003: 83-88 |
19 | EE | C. Roman, Salvador Mir, Benoît Charlot: Building an analogue fault simulation tool and its application to MEMS. Microelectronics Journal 34(10): 897-906 (2003) |
2002 | ||
18 | EE | Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim: SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? VTS 2002: 449-450 |
2001 | ||
17 | EE | Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois: Electrically Induced Stimuli For MEMS Self-Test. VTS 2001: 210-217 |
16 | EE | Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois: Generation of Electrically Induced Stimuli for MEMS Self-Test. J. Electronic Testing 17(6): 459-470 (2001) |
2000 | ||
15 | EE | Salvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz: Towards design and validation of mixed-technology SOCs. ACM Great Lakes Symposium on VLSI 2000: 29-33 |
14 | EE | Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois: Design of self-checking fully differential circuits and boards. IEEE Trans. VLSI Syst. 8(2): 113-128 (2000) |
13 | EE | Salvador Mir, Benoît Charlot, Bernard Courtois: Extending Fault-Based Testing to Microelectromechanical Systems. J. Electronic Testing 16(3): 279-288 (2000) |
1999 | ||
12 | Benoît Charlot, Salvador Mir, Érika F. Cota, Marcelo Lubaszewski, Bernard Courtois: Fault modeling of suspended thermal MEMS. ITC 1999: 319-328 | |
11 | Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner: Design and Test of MEMs. VLSI Design 1999: 270- | |
10 | EE | Salvador Mir, Benoît Charlot: On the Integration of Design and Test for Chips Embedding MEMS. IEEE Design & Test of Computers 16(4): 28-38 (1999) |
1998 | ||
9 | EE | Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas: Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. DATE 1998: 810-814 |
8 | EE | A. Castillejo, D. Veychard, Salvador Mir, Jean-Michel Karam, Bernard Courtois: Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems. ITC 1998: 541-550 |
1997 | ||
7 | EE | Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas: SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. DAC 1997: 281-286 |
1996 | ||
6 | EE | Marcelo Lubaszewski, Salvador Mir, Leandro Pulz: ABILBO: Analog BuILt-in Block Observer. ICCAD 1996: 600-603 |
5 | EE | Salvador Mir, Marcelo Lubaszewski, Bernard Courtois: Unified built-in self-test for fully differential analog circuits. J. Electronic Testing 9(1-2): 135-151 (1996) |
4 | EE | Salvador Mir, Marcelo Lubaszewski, Bernard Courtois: Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets. J. Electronic Testing 9(1-2): 43-57 (1996) |
1995 | ||
3 | EE | Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois: Analog checkers with absolute and relative tolerances. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 607-612 (1995) |
1994 | ||
2 | EE | Salvador Mir, Nick Filer: Re-engineering hardware specifications by exploiting design semantics. EURO-DAC 1994: 336-341 |
1 | EE | Salvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois: Built-in self-test and fault diagnosis of fully differential analogue circuits. ICCAD 1994: 486-490 |