Steve Furber
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
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52 | EE | Shufan Yang, Steve Furber, Yebin Shi, Luis A. Plana: An admission control system for QoS provision on a best-effort GALS interconnect. ACSD 2008: 200-207 |
51 | EE | Alexander D. Rast, Shufan Yang, Mukaram Khan, Stephen B. Furber: Virtual synaptic interconnect using an asynchronous network-on-chip. IJCNN 2008: 2727-2734 |
50 | EE | Xin Jin, Stephen B. Furber, John V. Woods: Efficient modelling of spiking neural networks on a scalable chip multiprocessor. IJCNN 2008: 2812-2819 |
49 | EE | M. M. Khan, D. R. Lester, Luis A. Plana, Alexander D. Rast, X. Jin, E. Painkras, Stephen B. Furber: SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. IJCNN 2008: 2849-2856 |
48 | EE | Luis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu: An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. NOCS 2008: 215-216 |
47 | EE | Steve Furber, Steve Temple: Neural Systems Engineering. Computational Intelligence: A Compendium 2008: 763-796 |
46 | EE | Steve Furber: The Future of Computer Technology and its Implications for the Computer Industry. Comput. J. 51(6): 735-740 (2008) |
2007 | ||
45 | EE | Jo C. Ebergen, Steve Furber, Arash Saifhashemi: Notes On Pulse Signaling. ASYNC 2007: 15-24 |
44 | EE | Luis A. Plana, Stephen B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang: A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Design & Test of Computers 24(5): 454-463 (2007) |
43 | EE | Stephen B. Furber, G. Brown, Joy Bose, J. Mike Cumpstey, P. Marshall, Jonathan L. Shapiro: Sparse Distributed Memory Using Rank-Order Neural Codes. IEEE Transactions on Neural Networks 18(3): 648-659 (2007) |
2006 | ||
42 | EE | Steve Furber: Living with Failure: Lessons from Nature? European Test Symposium 2006: 4-8 |
41 | EE | Stephen B. Furber, Steve Temple, A. Brown: On-chip and inter-chip networks for modeling large-scale neural systems. ISCAS 2006 |
40 | EE | Yijun Liu, Steve Furber, Zhenkun Li: The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing. PATMOS 2006: 425-438 |
39 | EE | Joy Bose, Stephen B. Furber, Jonathan L. Shapiro: An associative memory for the on-line recognition and prediction of temporal sequences CoRR abs/cs/0611020: (2006) |
2005 | ||
38 | EE | Joy Bose, Stephen B. Furber, Jonathan L. Shapiro: A Spiking Neural Sparse Distributed Memory Implementation for Learning and Predicting Temporal Sequences. ICANN (1) 2005: 115-120 |
37 | EE | Yijun Liu, Stephen B. Furber: A Low Power Embedded Dataflow Coprocessor. ISVLSI 2005: 246-247 |
36 | EE | Yijun Liu, Stephen B. Furber: The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. PATMOS 2005: 647-656 |
35 | EE | Joy Bose, Stephen B. Furber, Jonathan L. Shapiro: A System for Transmitting a Coherent Burst of Activity Through a Network of Spiking Neurons. WIRN/NAIS 2005: 44-48 |
2004 | ||
34 | EE | W. J. Bainbridge, Luis A. Plana, Stephen B. Furber: The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. DATE 2004: 274-279 |
33 | EE | Yijun Liu, Stephen B. Furber: The design of a low power asynchronous multiplier. ISLPED 2004: 301-306 |
32 | EE | Yijun Liu, Stephen B. Furber: Minimizing the Power Consumption of an Asynchronous Multiplier. PATMOS 2004: 289-300 |
31 | EE | Alexandre Yakovlev, Stephen B. Furber, René Krenz, Alexandre V. Bystrov: Design and Analysis of a Self-Timed Duplex Communication System. IEEE Trans. Computers 53(7): 798-814 (2004) |
30 | EE | Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple: Sparse distributed memory using N-of-M codes. Neural Networks 17(10): 1437-1451 (2004) |
2003 | ||
29 | EE | W. J. Bainbridge, W. B. Toms, David A. Edwards, Stephen B. Furber: Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. ASYNC 2003: 132-140 |
28 | EE | Z. C. Yu, Stephen B. Furber, Luis A. Plana: An Investigation into the Security of Self-Timed Circuits. ASYNC 2003: 206-215 |
27 | EE | T. Felicijan, Stephen B. Furber: An asynchronous ternary logic signaling system. IEEE Trans. VLSI Syst. 11(6): 1114-1119 (2003) |
26 | EE | Daranee Hormdee, Jim D. Garside, Stephen B. Furber: An asynchronous copy-back cache architecture. Microprocessors and Microsystems 27(10): 485-500 (2003) |
25 | EE | Steve Furber: Editorial. Microprocessors and Microsystems 27(9): 407-408 (2003) |
2002 | ||
24 | EE | Daranee Hormdee, Jim D. Garside, Stephen B. Furber: An Asynchronous Victim Cache. DSD 2002: 4-11 |
23 | EE | Stephen B. Furber: Validating the AMULET Microprocessors. Comput. J. 45(1): 19-26 (2002) |
22 | EE | John Bainbridge, Stephen B. Furber: Chain: A Delay-Insensitive Chip Area Interconnect. IEEE Micro 22(5): 16-23 (2002) |
2001 | ||
21 | EE | W. J. Bainbridge, Stephen B. Furber: Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. ASYNC 2001: 118-126 |
20 | EE | P. A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber: A Low-Power Self-Timed Viterbi Decoder. ASYNC 2001: 15-24 |
19 | EE | Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple: Power Management in the Amulet Microprocessors. IEEE Design & Test of Computers 18(2): 42-52 (2001) |
2000 | ||
18 | EE | Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, J. V. Woods, Jianwei Liu, O. Petli: AMULET3i - An Asynchronous System-on-Chip. ASYNC 2000: 162-175 |
17 | EE | Stephen B. Furber, David A. Edwards, Jim D. Garside: AMULET3: A 100 MIPS Asynchronous Embedded Processor. ICCD 2000: 329-334 |
1999 | ||
16 | EE | Jim D. Garside, Stephen B. Furber, S.-H. Chung: AMULET3 Revealed. ASYNC 1999: 51-59 |
1998 | ||
15 | EE | W. J. Bainbridge, Stephen B. Furber: Asynchronous Macrocell Interconnect using MARBLE. ASYNC 1998: 122-132 |
14 | EE | Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen: The Design of an Asynchronous VHDL Synthesizer. DATE 1998: 44-51 |
13 | Philip Endecott, Stephen B. Furber: Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language. ESM 1998: 39-43 | |
1997 | ||
12 | EE | O. A. Petlin, Stephen B. Furber: Built-In Self-Testing of Micropipelines. ASYNC 1997: 22-29 |
11 | EE | Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver: AMULET2e: An Asynchronous Embedded Controller. ASYNC 1997: 290- |
10 | J. V. Woods, P. Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple: AMULET1: A Asynchronous ARM Microprocessor. IEEE Trans. Computers 46(4): 385-398 (1997) | |
1996 | ||
9 | Stephen B. Furber: The Return of Asynchronous Logic. ITC 1996: 938 | |
8 | EE | Stephen B. Furber, P. Day: Four-phase micropipeline latch control circuits. IEEE Trans. VLSI Syst. 4(2): 247-253 (1996) |
1995 | ||
7 | EE | O. A. Petlin, Stephen B. Furber: Scan testing of asynchronous sequential circuits. Great Lakes Symposium on VLSI 1995: 224-229 |
6 | EE | O. A. Petlin, Stephen B. Furber: Scan testing of micropipelines. VTS 1995: 296-303 |
1994 | ||
5 | Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods: AMULET1: A Micropipelined ARM. COMPCON 1994: 476-485 | |
4 | Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, J. V. Woods: The Design and Evaluation of an Asynchronous Microprocessor. ICCD 1994: 217-220 | |
1993 | ||
3 | Stephen B. Furber, Martyn Edwards: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993 North-Holland 1993 | |
2 | Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods: A micropipelined ARM. VLSI 1993: 211-220 | |
1992 | ||
1 | N. C. Paver, P. Day, Stephen B. Furber, Jim D. Garside, J. V. Woods: Register Locking in an Asynchronous Microprocessor. ICCD 1992: 351-355 |