| 2009 |
|---|
| 58 | EE | Awadhesh Kumar Singh,
Rohit Bhat,
Anshul Kumar:
An Index-Based Mobile Checkpointing and Recovery Algorithm.
ICDCN 2009: 200-205 |
| 2008 |
|---|
| 57 | EE | Nagaraju Pothineni,
Anshul Kumar,
Kolin Paul:
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.
VLSI Design 2008: 261-266 |
| 56 | EE | Nagaraju Pothineni,
Anshul Kumar,
Kolin Paul:
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.
VLSI Design 2008: 348-353 |
| 2007 |
|---|
| 55 | | Nagaraju Pothineni,
Anshul Kumar,
Kolin Paul:
Recurring Pattern Identification and its Application to Instruction Set Extension.
CDES 2007: 67-73 |
| 54 | EE | Neeraj Goel,
Anshul Kumar,
Preeti Ranjan Panda:
Power Reduction in VLIW Processor with Compiler Driven Bypass Network.
VLSI Design 2007: 233-238 |
| 53 | EE | Nagaraju Pothineni,
Anshul Kumar,
Kolin Paul:
Application Specific Datapath Extension with Distributed I/O Functional Units.
VLSI Design 2007: 551-558 |
| 52 | EE | Anup Gangwar,
M. Balakrishnan,
Anshul Kumar:
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.
ACM Trans. Design Autom. Electr. Syst. 12(1): (2007) |
| 51 | EE | Anup Gangwar,
M. Balakrishnan,
Preeti Ranjan Panda,
Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
International Journal of Parallel Programming 35(6): 507-527 (2007) |
| 2006 |
|---|
| 50 | EE | Basant Kumar Dwivedi,
Arun Kejariwal,
M. Balakrishnan,
Anshul Kumar:
Rapid Resource-Constrained Hardware Performance Estimation.
IEEE International Workshop on Rapid System Prototyping 2006: 40-46 |
| 2005 |
|---|
| 49 | EE | Anup Gangwar,
M. Balakrishnan,
Preeti Ranjan Panda,
Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
DATE 2005: 730-735 |
| 48 | EE | Venkat Rao,
Gaurav Singhal,
Anshul Kumar,
Nicolas Navet:
Battery Model for Embedded Systems.
VLSI Design 2005: 105-110 |
| 47 | EE | Manoj Kumar Jain,
M. Balakrishnan,
Anshul Kumar:
Integrated On-Chip Storage Evaluation in ASIP Synthesis.
VLSI Design 2005: 274-279 |
| 2004 |
|---|
| 46 | EE | Basant Kumar Dwivedi,
Anshul Kumar,
M. Balakrishnan:
Automatic synthesis of system on chip multiprocessor architectures for process networks.
CODES+ISSS 2004: 60-65 |
| 45 | EE | Diviya Jain,
Anshul Kumar,
Laura Pozzi,
Paolo Ienne:
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.
SCOPES 2004: 17-32 |
| 44 | EE | Venkat Rao,
Gaurav Singhal,
Anshul Kumar:
Real Time Dynamic Voltage Scaling For Embedded Systems.
VLSI Design 2004: 650-653 |
| 43 | EE | Sourabh Saluja,
Anshul Kumar:
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture.
VLSI Design 2004: 761-764 |
| 42 | EE | Basant Kumar Dwivedi,
Anshul Kumar,
M. Balakrishnan:
Synthesis of Application Specific Multiprocessor Architectures for Process Networks.
VLSI Design 2004: 780-783 |
| 41 | EE | Manoj Kumar Jain,
M. Balakrishnan,
Anshul Kumar:
An efficient technique for exploring register file size in ASIP design.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1693-1699 (2004) |
| 2003 |
|---|
| 40 | EE | Manoj Kumar Jain,
M. Balakrishnan,
Anshul Kumar:
Exploring Storage Organization in ASIP Synthesis.
DSD 2003: 120-127 |
| 39 | EE | Rohini Krishnan,
Om Prakash Gangwal,
Jos T. J. van Eijndhoven,
Anshul Kumar:
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.
VLSI Design 2003: 177-182 |
| 38 | EE | Amarjeet Singh,
Amit Chhabra,
Anup Gangwar,
Basant Kumar Dwivedi,
M. Balakrishnan,
Anshul Kumar:
SoC Synthesis with Automatic Hardware Software Interface Generation.
VLSI Design 2003: 585- |
| 2002 |
|---|
| 37 | EE | Manoj Kumar Jain,
M. Balakrishnan,
Anshul Kumar:
An efficient technique for exploring register file size in ASIP synthesis.
CASES 2002: 252-261 |
| 36 | EE | Sushil Chandra Jain,
Anshul Kumar,
Shashi Kumar:
Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing.
IEEE International Workshop on Rapid System Prototyping 2002: 66- |
| 35 | EE | M. Balakrishnan,
Anshul Kumar,
C. P. Joshi:
A New Performance Evaluation Approach for System Level Design Space Exploration.
ISSS 2002: 180-185 |
| 34 | EE | M. Balakrishnan,
Anshul Kumar,
Paolo Ienne,
Anup Gangwar,
Bhuvan Middha:
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.
ISSS 2002: 2-7 |
| 33 | EE | Vishal P. Bhatt,
M. Balakrishnan,
Anshul Kumar:
Exploring the Number of Register Windows in ASIP Synthesis.
VLSI Design 2002: 233-238 |
| 32 | EE | Murali Mohan,
Rohini Krishnan,
Anshul Kumar,
M. Balakrishnan:
A New Divide and Conquer Method for Achieving High Speed Division in Hardware.
VLSI Design 2002: 535-540 |
| 2001 |
|---|
| 31 | EE | Anupam Rastogi,
M. Balakrishnan,
Anshul Kumar:
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study.
VLSI Design 2001: 23-28 |
| 30 | EE | Ram Lakhan Gupta,
Anshul Kumar,
Aalbert Van Der Werf,
Natalino G. Busa:
Synthesizing A Long Latency Unit Within Vliw Processor.
VLSI Design 2001: 460- |
| 29 | EE | Manoj Kumar Jain,
M. Balakrishnan,
Anshul Kumar:
ASIP Design Methodologies : Survey and Issues.
VLSI Design 2001: 76- |
| 2000 |
|---|
| 28 | EE | Sushil Chandra Jain,
Anshul Kumar,
Shashi Kumar:
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.
FPL 2000: 201-210 |
| 27 | EE | Sushil Chandra Jain,
Shashi Kumar,
Anshul Kumar:
Evaluation of Various Routing Architectures for Multi-FPGA Boards.
VLSI Design 2000: 262-267 |
| 26 | EE | Arvind Rajawat,
M. Balakrishnan,
Anshul Kumar:
nterface Synthesis: Issues and Approaches.
VLSI Design 2000: 92 |
| 25 | EE | Johnny Öberg,
Anshul Kumar,
Ahmed Hemani:
Grammar-based hardware synthesis from port-size independent specifications.
IEEE Trans. VLSI Syst. 8(2): 184-194 (2000) |
| 1999 |
|---|
| 24 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
Built-in Self Test Based on Multiple On-Chip Signature Checking.
J. Electronic Testing 14(3): 227-244 (1999) |
| 1998 |
|---|
| 23 | EE | Johnny Öberg,
Ahmed Hemani,
Anshul Kumar:
Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols.
DATE 1998: 596- |
| 22 | EE | Johnny Öberg,
Anshul Kumar,
Ahmed Hemani:
Specification of Exception Handling in Grammar-Based Hardware Synthesis.
EUROMICRO 1998: 10038-10041 |
| 21 | | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
Hybrid Testing Schemes Based on Mutual and Signature Testing.
VLSI Design 1998: 293- |
| 20 | EE | Johnny Öberg,
Axel Jantsch,
Anshul Kumar:
An Object-Oriented Concept for Intelligent Library Functions.
VLSI Design 1998: 355-358 |
| 19 | | Sitanshu Jain,
M. Balakrishnan,
Anshul Kumar,
Shashi Kumar:
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.
VLSI Design 1998: 400-405 |
| 18 | | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
On-Chip Signature Checking for Embedded Memories.
VLSI Design 1998: 558-563 |
| 17 | EE | A. R. Naseer,
M. Balakrishnan,
Anshul Kumar:
Direct mapping of RTL structures onto LUT-based FPGA's.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(7): 624-631 (1998) |
| 16 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems.
J. Electronic Testing 12(3): 199-216 (1998) |
| 1997 |
|---|
| 15 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
A scheme for multiple on-chip signature checking for embedded SRAMs.
ED&TC 1997: 625 |
| 14 | EE | A. R. Naseer,
M. Balakrishnan,
Anshul Kumar:
Optimal Clock Period for Synthesized Data Paths.
VLSI Design 1997: 134-139 |
| 13 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
Efficient Implementation of Multiple On-Chip Signature Checking.
VLSI Design 1997: 297-302 |
| 1996 |
|---|
| 12 | EE | Johnny Öberg,
Anshul Kumar,
Ahmed Hemani:
Grammar-Based Hardware Synthesis of Data Communication Protocols.
ISSS 1996: 14-19 |
| 11 | EE | Mohammed Fadle Abdulla,
C. P. Ravikumar,
Anshul Kumar:
A Novel BIST Architecture With Built-in Self Check.
VLSI Design 1996: 57-60 |
| 1995 |
|---|
| 10 | | A. R. Naseer,
M. Balakrishnan,
Anshul Kumar:
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs.
FPL 1995: 139-148 |
| 9 | EE | B. M. Subraya,
Anshul Kumar,
Shashi Kumar:
An HOL based framework for design of correct high level synthesizers.
VLSI Design 1995: 249-254 |
| 8 | EE | Alok Kumar,
Anshul Kumar,
M. Balakrishnan:
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis.
VLSI Design 1995: 75-80 |
| 1994 |
|---|
| 7 | | A. R. Naseer,
M. Balakrishnan,
Anshul Kumar:
An Efficient Technique for Mapping RTL Structures onto FPGAs.
FPL 1994: 99-110 |
| 6 | | A. R. Naseer,
M. Balakrishnan,
Anshul Kumar:
FAST: FPGA Targeted RTL Structure Synthesis Technique.
VLSI Design 1994: 21-24 |
| 1993 |
|---|
| 5 | | C. S. Ajay,
M. Balakrishnan,
D. Harikrishna,
M. Karunakaran,
Anshul Kumar,
Shashi Kumar,
V. Mudgil,
A. R. Naseer:
High Level Design Experiences with IDEAS.
VLSI Design 1993: 110 |
| 4 | | M. V. Rao,
M. Balakrishnan,
Anshul Kumar:
DESSERT: Design Space Exploration of RT Level Components.
VLSI Design 1993: 299-304 |
| 1985 |
|---|
| 3 | EE | Kumar Ramayya,
Anshul Kumar,
Surendra Prasad:
An automated data path synthesizer for a canonic structure, implementable in VLSI.
DAC 1985: 381-387 |
| 2 | EE | Anjali Arya,
Anshul Kumar,
V. V. Swaminathan,
Amit Misra:
Automatic generation of digital system schematic diagrams.
DAC 1985: 388-395 |
| 1980 |
|---|
| 1 | | Anshul Kumar,
P. C. P. Bhatt:
A Structured Language for CAD of Digital Systems.
ISCA 1980: 308-316 |
