| 2005 |
|---|
| 8 | EE | Antoni Portero,
Lluis Ribas,
Jordi Carrabina:
Hardware Synthesis of Parallel Machines from SystemC.
FDL 2005: 353-361 |
| 1999 |
|---|
| 7 | EE | Lluis Ribas,
Jordi Carrabina:
Digital MOS Circuit Partitioning with Symbolic Modeling.
DATE 1999: 503-508 |
| 1998 |
|---|
| 6 | EE | Lluis Ribas,
Jordi Carrabina:
On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits.
DATE 1998: 624- |
| 1997 |
|---|
| 5 | | Jordi Riera,
Lluis Ribas,
A. Josep Velasco,
Jordi Carrabina:
Deriving cost functions from cell libraries and real ICs to allow real area-power-delay trade-off in early stages of logic synthesis.
Journal of Systems Architecture 43(1-5): 119-122 (1997) |
| 1995 |
|---|
| 4 | EE | Lluis Ribas,
Jordi Carrabina:
Analysis of Switch-Level Faults by Symbolic Simulation.
DAC 1995: 352-357 |
| 3 | | Lluis Ribas,
Jordi Carrabina:
Symbolic Analysis for Fault Detection in Switch-Level Circuits.
ISCAS 1995: 1235-1238 |
| 1994 |
|---|
| 2 | | A. Josep Velasco,
Lluis Ribas,
Elena Valderrama,
R. Gracia:
A Fuzzy Rule Interpreter to Build Expert Systems Based on Fuzzy Logic. An Application in Company Diagnosis.
Fuzzy Days 1994: 433-438 |
| 1 | | Rafael Peset Llopis,
Lluis Ribas,
Jordi Carrabina:
Short Destabilizing Paths in Timing Verification.
ICCD 1994: 160-163 |
