2008 |
31 | EE | Matthias Krause,
Dominik Englert,
Oliver Bringmann,
Wolfgang Rosenstiel:
Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation.
CODES+ISSS 2008: 143-148 |
30 | EE | Jürgen Schnerr,
Oliver Bringmann,
Alexander Viehl,
Wolfgang Rosenstiel:
High-performance timing simulation of embedded software.
DAC 2008: 290-295 |
29 | EE | Alexander Viehl,
Björn Sander,
Oliver Bringmann,
Wolfgang Rosenstiel:
Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties.
FDL 2008: 105-110 |
28 | EE | Jochen Zimmermann,
Oliver Bringmann,
Joachim Gerlach,
Florian Schaefer,
Ulrich Nageldinger:
Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited).
FDL 2008: 227-232 |
2007 |
27 | EE | Axel Siebenborn,
Alexander Viehl,
Oliver Bringmann,
Wolfgang Rosenstiel:
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes.
ASP-DAC 2007: 32-37 |
26 | EE | Alexander Viehl,
Markus Schwarz,
Oliver Bringmann,
Wolfgang Rosenstiel:
Probabilistic performance risk analysis at system-level.
CODES+ISSS 2007: 185-190 |
25 | EE | Matthias Krause,
Oliver Bringmann,
André Hergenhan,
Gökhan Tabanoglu,
Wolfgang Rosenstiel:
Timing simulation of interconnected AUTOSAR software-components.
DATE 2007: 474-479 |
24 | EE | Timo Schönwald,
Jochen Zimmermann,
Oliver Bringmann,
Wolfgang Rosenstiel:
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures.
DSD 2007: 527-534 |
23 | EE | Alexander Viehl,
Markus Schwarz,
Oliver Bringmann,
Wolfgang Rosenstiel:
A Hybrid Approach for System-Level Design Evaluation.
IESS 2007: 165-178 |
22 | EE | Jürgen Schnerr,
Oliver Bringmann,
Wolfgang Rosenstiel:
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
CoRR abs/0710.4644: (2007) |
2006 |
21 | EE | Abdelmajid Bouajila,
Andreas Bernauer,
Andreas Herkersdorf,
Wolfgang Rosenstiel,
Oliver Bringmann,
Walter Stechele:
Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs.
BICC 2006: 107-113 |
20 | EE | Wolfgang Klingauf,
Robert Günzel,
Oliver Bringmann,
Pavel Parfuntseu,
Mark Burton:
GreenBus: a generic interconnect fabric for transaction level modelling.
DAC 2006: 905-910 |
19 | EE | Alexander Viehl,
Timo Schönwald,
Oliver Bringmann,
Wolfgang Rosenstiel:
Formal performance analysis and simulation of UML/SysML models for ESL design.
DATE 2006: 242-247 |
18 | | Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel,
Abdelmajid Bouajila,
Walter Stechele,
Andreas Herkersdorf:
An Architecture for Runtime Evaluation of SoC Reliability.
GI Jahrestagung (1) 2006: 177- |
17 | EE | Abdelmajid Bouajila,
Johannes Zeppenfeld,
Walter Stechele,
Andreas Herkersdorf,
Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel:
Organic Computing at the System on Chip Level.
VLSI-SoC 2006: 338-341 |
2005 |
16 | | Gabriel Lipsa,
Andreas Herkersdorf,
Wolfgang Rosenstiel,
Oliver Bringmann,
Walter Stechele:
Towards a Framework and a Design Methodology for Autonomous SoC.
ARCS Workshops 2005: 101-108 |
15 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Axel Siebenborn:
Conflict analysis in multiprocess synthesis for optimized system integration.
CODES+ISSS 2005: 15-20 |
14 | EE | Jürgen Schnerr,
Oliver Bringmann,
Wolfgang Rosenstiel:
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs.
DATE 2005: 792-797 |
13 | EE | Axel Braun,
Joachim Gerlach,
Wolfgang Rosenstiel,
Axel Siebenborn,
Oliver Bringmann:
SystemC-Based Communication and Performance Analysis.
FDL 2005: 33-48 |
12 | EE | Gabriel Lipsa,
Andreas Herkersdorf,
Wolfgang Rosenstiel,
Oliver Bringmann,
Walter Stechele:
Towards a Framework and a Design Methodology for Autonomic SoC.
ICAC 2005: 391-392 |
2004 |
11 | EE | Axel Siebenborn,
Oliver Bringmann,
Wolfgang Rosenstiel:
Communication Analysis for System-On-Chip Design.
DATE 2004: 648-655 |
10 | EE | Axel Siebenborn,
Oliver Bringmann,
Wolfgang Rosenstiel:
Communication Analysis for Network-on-Chip Design.
PARELEC 2004: 315-320 |
2002 |
9 | EE | Axel Siebenborn,
Oliver Bringmann,
Wolfgang Rosenstiel:
Worst-case performance analysis of parallel, communicating software processes.
CODES 2002: 37-42 |
8 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Carsten Menn:
Controller Estimation for FPGA Target Architectures during High-Level Synthesis.
ISSS 2002: 56-61 |
2000 |
7 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Carsten Menn:
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation.
DATE 2000: 326-332 |
1999 |
6 | | Oliver Bringmann,
Wolfgang Rosenstiel:
Hierarchische Synthese für die Emulation von integrierten Steuerungssystemen.
GI Jahrestagung 1999: 146-153 |
5 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Annette Muth,
Georg Färber,
Frank Slomka,
Richard Hofmann:
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping.
IEEE International Workshop on Rapid System Prototyping 1999: 114-119 |
1998 |
4 | EE | Oliver Bringmann,
Wolfgang Rosenstiel:
Cross-Level Hierarchical High-Level Synthesis.
DATE 1998: 451-456 |
3 | EE | Oliver Bringmann,
Wolfgang Rosenstiel,
Dirk Reichardt:
Synchronization Detection for Multi-Process Hierarchical Synthesis.
ISSS 1998: 105-110 |
1997 |
2 | EE | Oliver Bringmann,
Wolfgang Rosenstiel:
Resource sharing in hierarchical synthesis.
ICCAD 1997: 318-325 |
1995 |
1 | EE | Ulrich Weinmann,
Oliver Bringmann,
Wolfgang Rosenstiel:
Device selection for system partitioning.
EURO-DAC 1995: 2-7 |