| 2009 |
|---|
| 72 | EE | Jungsoo Kim,
Seungyong Oh,
Sungjoo Yoo,
Chong-Min Kyung:
An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 568-581 (2009) |
| 2008 |
|---|
| 71 | EE | Seungyong Oh,
Jungsoo Kim,
Seonpil Kim,
Chong-Min Kyung:
Task partitioning algorithm for intra-task dynamic voltage scaling.
ISCAS 2008: 1228-1231 |
| 70 | EE | Seonpil Kim,
Heejun Shim,
Chong-Min Kyung:
Data Reuse method between Heterogeneous Partitions (DRHP) in H.264/AVC motion compensator.
ISCAS 2008: 3506-3509 |
| 2007 |
|---|
| 69 | EE | Kyungsu Kang,
Jungsoo Kim,
Heejun Shim,
Chong-Min Kyung:
Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor.
ACM Great Lakes Symposium on VLSI 2007: 594-599 |
| 68 | EE | Heejun Shim,
Kyungsu Kang,
Chong-Min Kyung:
Search Area Selective Reuse Algorithm in Motion Estimation.
ICME 2007: 1611-1614 |
| 67 | EE | Woong Hwangbo,
Jaemoon Kim,
Chong-Min Kyung:
A High-Performance 2-D Inverse Transform Architecture for the H.264/AVC Decoder.
ISCAS 2007: 1613-1616 |
| 66 | EE | Sung-Joon Jang,
Moo-Kyoung Chung,
Jaemoon Kim,
Chong-Min Kyung:
Cache Miss-Aware Dynamic Stack Allocation.
ISCAS 2007: 3494-3497 |
| 65 | EE | Jaemoon Kim,
Sangkown Na,
Chong-Min Kyung:
A low-power deblocking filter architecture for H.264 advanced video coding.
VLSI-SoC 2007: 190-193 |
| 64 | EE | Jungsoo Kim,
Kyungsu Kang,
Heejun Shim,
Woong Hwangbo,
Chong-Min Kyung:
Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model.
VLSI-SoC 2007: 224-229 |
| 63 | EE | Jae-Gon Lee,
Moo-Kyoung Chung,
Ki-Yong Ahn,
Sang-Heon Lee,
Chong-Min Kyung:
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation
CoRR abs/0710.4701: (2007) |
| 2006 |
|---|
| 62 | EE | Moo-Kyoung Chung,
Chong-Min Kyung:
Improving Lookahead in Parallel Multiprocessor Simulation Using Dynamic Execution Path Prediction.
PADS 2006: 11-18 |
| 61 | EE | Moo-Kyoung Chung,
Chong-Min Kyung:
Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead.
IEEE Trans. Computers 55(2): 125-136 (2006) |
| 60 | EE | Moo-Kyung Kang,
Chong-Min Kyung:
Three-Stage Clos-Network Switch Architecture with Buffered Center Stage for Multi-Class Traffic.
Journal of Circuits, Systems, and Computers 15(2): 263-276 (2006) |
| 2005 |
|---|
| 59 | EE | Jae-Gon Lee,
Wooseung Yang,
Young-Su Kwon,
Young-Il Kim,
Chong-Min Kyung:
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.
ASP-DAC 2005: 499-502 |
| 58 | EE | Jae-Gon Lee,
Moo-Kyoung Chung,
Ki-Yong Ahn,
Sang-Heon Lee,
Chong-Min Kyung:
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation.
DATE 2005: 384-389 |
| 57 | EE | Moo-Kyoung Chung,
Heejun Shim,
Chong-Min Kyung:
Performance Improvement of Multiprocessor Simulation by Optimizing Synchronization a Communication.
IEEE International Workshop on Rapid System Prototyping 2005: 158-164 |
| 56 | EE | Young-Su Kwon,
Chong-Min Kyung:
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1444-1456 (2005) |
| 55 | EE | Wooseung Yang,
Chong-Min Kyung:
Conscep: a Configurable Soc Emulation Platform for C-based Fast Prototyping.
Journal of Circuits, Systems, and Computers 14(1): 137-158 (2005) |
| 54 | EE | Ju Hwan Yi,
Chong-Min Kyung:
Symbolic Reachability Analysis for Multiple-clock System Design.
Journal of Circuits, Systems, and Computers 14(3): 533-552 (2005) |
| 2004 |
|---|
| 53 | EE | Young-Il Kim,
Bong-Il Park,
Jae-Gon Lee,
Chong-Min Kyung:
SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine.
ASP-DAC 2004: 734-736 |
| 52 | EE | Young-Su Kwon,
Jae-Gon Lee,
Chong-Min Kyung:
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation.
ASP-DAC 2004: 806-811 |
| 51 | EE | Young-Il Kim,
Woo-Seung Yang,
Young-Su Kwon,
Chong-Min Kyung:
Communication-efficient hardware acceleration for fast functional simulation.
DAC 2004: 293-298 |
| 50 | EE | Young-Su Kwon,
Young-Il Kim,
Chong-Min Kyung:
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph.
DAC 2004: 45-48 |
| 49 | EE | Young-Su Kwon,
Chong-Min Kyung:
Functional Coverage Metric Generation from Temporal Event Relation Graph.
DATE 2004: 670-671 |
| 48 | EE | Young-Il Kim,
Chong-Min Kyung:
Automatic translation of behavioral testbench for fully accelerated simulation.
ICCAD 2004: 218-221 |
| 47 | EE | Moo-Kyoung Chung,
Chong-Min Kyung:
Improvement of Compiled Instruction Set Simulator by Increasing Flexibility a.
IEEE International Workshop on Rapid System Prototyping 2004: 38-44 |
| 46 | EE | Young-Il Kim,
Chong-Min Kyung:
TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification.
IEEE Design & Test of Computers 21(6): 484-493 (2004) |
| 45 | EE | Nak-Woong Eum,
Taewhan Kim,
Chong-Min Kyung:
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
IEEE Trans. Computers 53(7): 829-842 (2004) |
| 44 | EE | Young-Su Kwon,
Chong-Min Kyung:
Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture.
Microprocessors and Microsystems 28(5-6): 341-350 (2004) |
| 2003 |
|---|
| 43 | EE | Young-Su Kwon,
Bong-Il Park,
Chong-Min Kyung:
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture.
ICCD 2003: 419-425 |
| 42 | EE | Byoung-Woon Kim,
Chong-Min Kyung:
System-on-Chip design using intellectual properties with imprecise design costs.
ISCAS (5) 2003: 625-628 |
| 41 | | Young-Su Kwon,
Woo-Seung Yang,
Chong-Min Kyung:
Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection.
VLSI-SOC 2003: 123-128 |
| 2002 |
|---|
| 40 | EE | You-Sung Chang,
Chong-Min Kyung:
Conforming block inversion for low power memory.
IEEE Trans. VLSI Syst. 10(1): 15-19 (2002) |
| 39 | EE | Byoung-Woon Kim,
Chong-Min Kyung:
Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis.
IEEE Trans. VLSI Syst. 10(3): 240-252 (2002) |
| 38 | EE | Seungjong Lee,
Ando Ki,
In-Cheol Park,
Chong-Min Kyung:
Interface synthesis between software chip model and target board.
Journal of Systems Architecture 48(1-3): 49-57 (2002) |
| 2001 |
|---|
| 37 | EE | Nak-Woong Eum,
Taewhan Kim,
Chong-Min Kyung:
An accurate evaluation of routing density for symmetrical FPGAs.
ACM Great Lakes Symposium on VLSI 2001: 51-55 |
| 36 | EE | Woo-Seung Yang,
In-Cheol Park,
Chong-Min Kyung:
Low-power high-level synthesis using latches.
ASP-DAC 2001: 462-466 |
| 35 | EE | Nak-Woong Eum,
Taewhan Kim,
Chong-Min Kyung:
A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
ICCAD 2001: 137-143 |
| 2000 |
|---|
| 34 | EE | Sang-Joon Nam,
Jun-Hee Lee,
Byoung-Woon Kim,
Yeon-Ho Im,
Young-Su Kwon,
Kyong-Gu Kang,
Chong-Min Kyung:
Fast development of source-level debugging system using hardware emulation (short paper).
ASP-DAC 2000: 401-404 |
| 33 | EE | Young-Su Kwon,
In-Cheol Park,
Chong-Min Kyung:
A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics.
ASP-DAC 2000: 559-564 |
| 32 | | Moo-Kyung Kang,
Ju Hwan Yi,
You-Sung Chang,
Chong-Min Kyung:
Switch Expansion Architecture Using Local Switching Network.
ICC (3) 2000: 1426-1429 |
| 31 | EE | Bong-Il Park,
Hoon Choi,
In-Cheol Park,
Chong-Min Kyung:
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies.
ICCD 2000: 519-524 |
| 30 | | Young-Su Kwon,
In-Cheol Park,
Chong-Min Kyung:
Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization.
ICIP 2000 |
| 29 | EE | Jin-Hyuk Yang,
Byoung-Woon Kim,
Sang-Joon Nam,
Young-Su Kwon,
Dae-Hyun Lee,
Jong-Yeol Lee,
Chan-Soo Hwang,
Yong-Hoon Lee,
Seung Ho Hwang,
In-Cheol Park,
Chong-Min Kyung:
MetaCore: an application-specific programmable DSP development system.
IEEE Trans. VLSI Syst. 8(2): 173-183 (2000) |
| 1999 |
|---|
| 28 | EE | Young-Su Kwon,
Bong-Il Park,
In-Cheol Park,
Chong-Min Kyung:
A New Single-Clock Flip-Clop for Half-Swing Clocking.
ASP-DAC 1999: 117-120 |
| 27 | EE | Hoon Choi,
Hansoo Kim,
In-Cheol Park,
Seung Ho Hwang,
Chong-Min Kyung:
Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods.
ASP-DAC 1999: 157-160 |
| 26 | EE | You-Sung Chang,
Seungjong Lee,
In-Cheol Park,
Chong-Min Kyung:
Verification of a Microprocessor Using Real World Applications.
DAC 1999: 181-184 |
| 25 | EE | Joon-Seo Yim,
Chong-Min Kyung:
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design.
DAC 1999: 485-490 |
| 24 | EE | Joon-Seo Yim,
Seong-Ok Bae,
Chong-Min Kyung:
A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs.
DAC 1999: 766-771 |
| 23 | EE | Hoon Choi,
Ju Hwan Yi,
Jong-Yeol Lee,
In-Cheol Park,
Chong-Min Kyung:
Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software.
DAC 1999: 939-944 |
| 22 | EE | You-Sung Chang,
Bong-Il Park,
In-Cheol Park,
Chong-Min Kyung:
Customization of a CISC Processor Core for Low-Power Applications.
ICCD 1999: 152- |
| 21 | EE | Bong-Il Park,
In-Cheol Park,
Chong-Min Kyung:
A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders.
ICCD 1999: 243- |
| 20 | EE | You-Sung Chang,
Bong-Il Park,
Chong-Min Kyung:
Conforming inverted data store for low power memory.
ISLPED 1999: 91-93 |
| 19 | | Hoon Choi,
Jong-Sun Kim,
Chi-Won Yoon,
In-Cheol Park,
Seung Ho Hwang,
Chong-Min Kyung:
Synthesis of Application Specific Instructions for Embedded DSP Software.
IEEE Trans. Computers 48(6): 603-614 (1999) |
| 1998 |
|---|
| 18 | | Jin-Hyuk Yang,
Byung-Woon Kim,
Sung-Won Seo,
Sang-Jun Nam,
Chang-Ho Ryu,
Jang-Ho Cho,
Chong-Min Kyung:
Metacore: A Configurable and Instruction Level Extensible DSP Core.
ASP-DAC 1998: 325-326 |
| 17 | EE | Namseung Kim,
Hoon Choi,
Seungjong Lee,
Seungwang Lee,
In-Cheol Park,
Chong-Min Kyung:
Virtual Chip: Making Functional Models Work on Real Target Systems.
DAC 1998: 170-173 |
| 16 | EE | Jin-Hyuk Yang,
Byoung-Woon Kim,
Sang-Jun Nam,
Jang-Ho Cho,
Sung-Won Seo,
Chang-Ho Ryu,
Young-Su Kwon,
Dae-Hyun Lee,
Jong-Yeol Lee,
Jong-Sun Kim,
Hyun-Dhong Yoon,
Jae-Yeol Kim,
Kun-Moo Lee,
Chan-Soo Hwang,
In-Hyung Kim,
Jun Sung Kim,
Kwang-Il Park,
Kyu Ho Park,
Yong-Hoon Lee,
Seung Ho Hwang,
In-Cheol Park,
Chong-Min Kyung:
MetaCore: An Application Specific DSP Development System.
DAC 1998: 800-803 |
| 15 | EE | Ju Hwan Yi,
Hoon Choi,
In-Cheol Park,
Seung Ho Hwang,
Chong-Min Kyung:
Multiple Behavior Module Synthesis Based on Selective Groupings.
DATE 1998: 384-388 |
| 14 | EE | Hoon Choi,
Seung Ho Hwang,
Chong-Min Kyung,
In-Cheol Park:
Synthesis of application specific instructions for embedded DSP software.
ICCAD 1998: 665-671 |
| 1997 |
|---|
| 13 | EE | Joon-Seo Yim,
Yoon-Ho Hwang,
Chang-Jae Park,
Hoon Choi,
Woo-Seung Yang,
Hun-Seung Oh,
In-Cheol Park,
Chong-Min Kyung:
A C-Based RTL Design Verification Methodology for Complex Microprocessor.
DAC 1997: 83-88 |
| 1996 |
|---|
| 12 | EE | Hyun-Joon Kim,
Chong-Min Kyung:
A new parallel ray-tracing system based on object decomposition.
The Visual Computer 12(5): 244-253 (1996) |
| 1994 |
|---|
| 11 | | In-Cheol Park,
Se-Kyoung Hong,
Chong-Min Kyung:
Two Complementary Approaches for Microcode Bit Optimization.
IEEE Trans. Computers 43(2): 234-239 (1994) |
| 1993 |
|---|
| 10 | EE | In-Cheol Park,
Chong-Min Kyung:
FAMOS: an efficient scheduling algorithm for high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1437-1448 (1993) |
| 1992 |
|---|
| 9 | EE | Chong-Min Kyung,
Josef Widder,
Dieter A. Mlynski:
Adaptive cluster growth: a new algorithm for circuit placement in rectilinear regions.
Computer-Aided Design 24(1): 27-35 (1992) |
| 8 | EE | Sung-Soo Kim,
Chong-Min Kyung:
Circuit placement on arbitrarily shaped regions using the self-organization principle.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(7): 844-854 (1992) |
| 7 | EE | Yeong-Yil Yang,
Chong-Min Kyung:
HALO: an efficient global placement strategy for standard cells.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 1024-1031 (1992) |
| 1991 |
|---|
| 6 | EE | In-Cheol Park,
Chong-Min Kyung:
Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis.
DAC 1991: 680-685 |
| 5 | | Sang-Gil Choi,
Chong-Min Kyung:
A Floorplanning Algorithm Using Rectangular Voronoi Diagram and Force-Directed Block Shaping.
ICCAD 1991: 56-59 |
| 1990 |
|---|
| 4 | EE | Chong-Min Kyung,
Josef Widder,
Dieter A. Mlynski:
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region.
EURO-DAC 1990: 191-195 |
| 3 | | Chong-Min Kyung,
Peter V. Kraus,
Dieter A. Mlynski:
Diffusion - An Analytic Procedure Applied to Macro Cell Placement.
ICCAD 1990: 102-105 |
| 2 | | Se-Kyoung Hong,
In-Cheol Park,
Chong-Min Kyung:
An O(n3logn)-Heuristic for Microcode Bit Optimization.
ICCAD 1990: 180-183 |
| 1 | | Peter V. Kraus,
Dieter A. Mlynski,
Chong-Min Kyung:
Diffusion - An analytic procedure applied to global macro cell placment.
Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme 1990: 64-74 |
