Mike Tien-Chien Lee

1998
17	EE	Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee: Functional Scan Chain Testing. DATE 1998: 278-
16	EE	Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee: Eliminating false loops caused by sharing in control path. ACM Trans. Design Autom. Electr. Syst. 3(3): 487-495 (1998)
15	EE	Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee: ATM switch design by high-level modeling, formal verification and high-level synthesi. ACM Trans. Design Autom. Electr. Syst. 3(4): 554-562 (1998)
14	EE	Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee: Test-point insertion: scan paths through functional logic. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 838-851 (1998)
13	EE	Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen: Cost-free scan: a low-overhead scan path design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 852-861 (1998)
1997
12	EE	Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng: A Test Synthesis Approach to Reducing BALLAST DFT Overhead. DAC 1997: 466-471
11	EE	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita: Power analysis and minimization techniques for embedded DSP software. IEEE Trans. VLSI Syst. 5(1): 123-135 (1997)
1996
10	EE	Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee: Test Point Insertion: Scan Paths through Combinational Logic. DAC 1996: 268-273
9	EE	Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita: Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. DAC 1996: 585-590
8	EE	Guido Araujo, Sharad Malik, Mike Tien-Chien Lee: Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. DAC 1996: 591-596
7	EE	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee: A novel methodology for transistor-level power estimation. ISLPED 1996: 67-72
6	EE	Alan Su, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee: Eliminating False Loops Caused by Sharing in Control Path. ISSS 1996: 39-44
5	EE	Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee: Instruction Level Power Analysis and Optimization of Software. VLSI Design 1996: 326-328
4	EE	Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee: Instruction level power analysis and optimization of software. VLSI Signal Processing 13(2-3): 223-238 (1996)
1995
3	EE	Vivek Tiwari, Mike Tien-Chien Lee: Power analysis of a 32-bit embedded microcontroller. ASP-DAC 1995
2	EE	Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen: Cost-free scan: a low-overhead scan path design methodology. ICCAD 1995: 528-533
1	EE	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita: Power analysis and low-power scheduling techniques for embedded DSP software. ISSS 1995: 110-115

Coauthor Index

1	Takashi Aikyo	[12]
2	Guido Araujo	[8]
3	Douglas Chang	[12] [17]
4	Ben Chen	[9]
5	Kuang-Chien Chen	[2] [7] [13]
6	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[7] [10] [12] [14] [17]
7	Masahiro Fujita	[1] [9] [11] [15]
8	Yu-Chin Hsu	[6] [9] [16]
9	Shi-Yu Huang	[7]
10	Chih-Chang Lin	[2] [10] [13] [14]
11	Ta-Yung Liu	[6] [16]
12	Sharad Malik	[1] [4] [5] [8] [11]
13	Malgorzata Marek-Sadowska	[2] [10] [12] [13] [14] [17]
14	Sreeranga P. Rajan	[15]
15	Alan Su	[6] [16]
16	Vivek Tiwari	[1] [3] [4] [5] [11]
17	Andrew Wolfe	[4] [5]
18	K. Yuan	[15]