2007 |
17 | EE | Maciej Brzozowski,
Vyacheslav N. Yarmolik:
Obfuscation as Intellectual Rights Protection in VHDL Language.
CISIM 2007: 337-340 |
16 | | Sergei B. Musin,
Alexander A. Ivaniuk,
Vyacheslav N. Yarmolik:
Multiple Errors Detection Technique for RAM.
DDECS 2007: 251-254 |
2002 |
15 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Alexander A. Ivaniuk,
Yuri V. Klimets,
Vyacheslav N. Yarmolik:
Efficient Online and Offline Testing of Embedded DRAMs.
IEEE Trans. Computers 51(7): 801-809 (2002) |
1999 |
14 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Vyacheslav N. Yarmolik:
Symmetric Transparent BIST for RAMs.
DATE 1999: 702-707 |
13 | EE | Vyacheslav N. Yarmolik,
I. V. Bykov,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.
EDCC 1999: 339-350 |
12 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Alexander A. Ivaniuk,
Yuri V. Klimets,
Vyacheslav N. Yarmolik:
Error Detecting Refreshment for Embedded DRAMs.
VTS 1999: 384-390 |
1998 |
11 | EE | Vyacheslav N. Yarmolik,
Yuri V. Klimets,
Serge N. Demidenko:
March PS(23N) Test for DRAM Pattern-Sensitive Faults.
Asian Test Symposium 1998: 354- |
10 | EE | Vyacheslav N. Yarmolik,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.
DATE 1998: 173-179 |
9 | EE | Serge N. Demidenko,
Vincenzo Piuri,
Vyacheslav N. Yarmolik,
A. Shmidman:
BIST Module for Mixed-Signal Circuits.
DFT 1998: 349- |
1997 |
8 | EE | A. J. van de Goor,
Georgi Gaydadjiev,
Vyacheslav N. Yarmolik,
V. G. Mikitjuk:
March LA: a test for linked memory faults.
ED&TC 1997: 627 |
1996 |
7 | EE | A. J. van de Goor,
G. N. Gaydadjiev,
V. G. Mikitjuk,
Vyacheslav N. Yarmolik:
March LR: a test for realistic linked faults.
VTS 1996: 272-280 |
6 | EE | Mark G. Karpovsky,
Vyacheslav N. Yarmolik:
Transparent random access memory testing for pattern sensitive faults.
J. Electronic Testing 9(3): 251-266 (1996) |
1995 |
5 | | O. Kebichi,
Michael Nicolaidis,
Vyacheslav N. Yarmolik:
Exact Aliasing Computation for RAM BIST.
ITC 1995: 13-22 |
1994 |
4 | | E. P. Kalosha,
Vyacheslav N. Yarmolik,
Mark G. Karpovsky:
Signature Testability of PLA.
FPL 1994: 335-337 |
3 | | Vyacheslav N. Yarmolik,
Michael Nicolaidis,
O. Kebichi:
Aliasing-free Signature Analysis for RAM BIST.
ITC 1994: 368-377 |
2 | | Mark G. Karpovsky,
Vyacheslav N. Yarmolik:
Transparent Memory Testing for Pattern-Sensitive Faults.
ITC 1994: 860-869 |
1 | EE | O. Kebichi,
Vyacheslav N. Yarmolik,
Michael Nicolaidis:
Zero aliasing ROM BIST.
J. Electronic Testing 5(4): 377-388 (1994) |