2007 |
12 | EE | Imad A. Ferzli,
Farid N. Najm,
Lars Kruse:
A geometric approach for early power grid verification using current constraints.
ICCAD 2007: 40-47 |
11 | EE | Imad A. Ferzli,
Farid N. Najm,
Lars Kruse:
Early power grid verification under circuit current uncertainties.
ISLPED 2007: 116-121 |
2002 |
10 | EE | Eike Schmidt,
Gerd von Cölln,
Lars Kruse,
Frans Theeuwen,
Wolfgang Nebel:
Memory power models for multilevel power estimation and optimization.
IEEE Trans. VLSI Syst. 10(2): 106-109 (2002) |
2001 |
9 | EE | Eike Schmidt,
Gerd Jochens,
Lars Kruse,
Frans Theeuwen,
Wolfgang Nebel:
Automatic nonlinear memory power modelling.
DATE 2001: 808 |
8 | | Ansgar Stammermann,
Lars Kruse,
Wolfgang Nebel,
Alexander Pratsch,
Eike Schmidt,
Milan Schulte,
Arne Schulz:
System level optimization and design space exploration for low power.
ISSS 2001: 142-146 |
7 | EE | Lars Kruse,
Eike Schmidt,
Gerd Jochens,
Ansgar Stammermann,
Arne Schulz,
Enrico Macii,
Wolfgang Nebel:
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs.
IEEE Trans. VLSI Syst. 9(1): 3-14 (2001) |
2000 |
6 | EE | Lars Kruse,
Eike Schmidt,
Gerd Jochens,
Ansgar Stammermann,
Wolfgang Nebel:
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints.
DATE 2000: 737 |
5 | EE | Lars Kruse,
Eike Schmidt,
Gerd Jochens,
Ansgar Stammermann,
Wolfgang Nebel:
Lower Bound Estimation for Low Power High-Level Synthesis.
ISSS 2000: 180-186 |
4 | EE | Gerd Jochens,
Lars Kruse,
Eike Schmidt,
Ansgar Stammermann,
Wolfgang Nebel:
Power Macro-Modelling for Firm-Macro.
PATMOS 2000: 24-35 |
1999 |
3 | EE | Gerd Jochens,
Lars Kruse,
Eike Schmidt,
Wolfgang Nebel:
A New Parameterizable Power Macro-Model for Datapath Components.
DATE 1999: 29- |
2 | EE | Lars Kruse,
Eike Schmidt,
Gerd Jochens,
Wolfgang Nebel:
Lower and upper bounds on the switching activity in scheduled data flow graphs.
ISLPED 1999: 115-120 |
1998 |
1 | EE | Dirk Rabe,
Gerd Jochens,
Lars Kruse,
Wolfgang Nebel,
Carl von Ossietzky:
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs.
DATE 1998: 356-361 |