Abhijit Dharchoudhury

1999
14	EE	Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441
13	EE	Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury: A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design 1999: 175-180
1998
12	EE	Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw: Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC 1998: 388-391
11	EE	Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden: Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC 1998: 738-743
10	EE	Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija: CMOS Combinational Circuit Sizing by Stage-wise Tapering. DATE 1998: 985-988
9	EE	David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards: Emerging power management tools for processor design. ISLPED 1998: 143-148
1997
8	EE	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw: Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662
7		Abhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning: Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148
1996
6	EE	Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang: iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. DAC 1996: 548-551
1995
5	EE	Abhijit Dharchoudhury, Sung-Mo Kang: Worst-case analysis and optimization of VLSI circuit performances. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 481-492 (1995)
1994
4	EE	Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee: Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. ICCAD 1994: 190-194
3	EE	Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel: Fast timing simulation of transient faults in digital circuits. ICCAD 1994: 719-722
1993
2	EE	Abhijit Dharchoudhury, Sung-Mo Kang: Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. DAC 1993: 154-158
1992
1	EE	Abhijit Dharchoudhury, Sung-Mo Kang: An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. DAC 1992: 704-709

Coauthor Index

1	David Bearden	[11]
2	David Blaauw (David T. Blaauw)	[7] [8] [9] [11] [12] [13] [14]
3	Hungse Cha	[3]
4	Yi-Kan Cheng	[6]
5	J. Dunning	[7]
6	Tim Edwards	[9] [12] [14]
7	Sergey Gavrilov	[8]
8	Alexey Glebov	[8]
9	Sung-Mo Kang	[1] [2] [3] [4] [5] [6]
10	K. H. (Kane) Kim (K. H. Kim, Kane Kim)	[4]
11	S. H. Lee	[4]
12	S. C. Moore	[8]
13	Joe Norton	[7] [12]
14	Chanhee Oh	[9] [14]
15	Rajendran Panda	[8] [9] [10] [11] [12] [14]
16	Janak H. Patel	[3]
17	Satyamurthy Pullela	[7] [8] [10]
18	Elyse Rosenbaum	[6]
19	Supamas Sirichotiyakul	[9] [14]
20	Savithri Sundareswaran	[13]
21	Chin-Chi Teng	[6]
22	Bogdan Tutuianu	[11]
23	Ravi Vaidyanathan	[11]
24	Gopal Vija	[10]
25	Gopalakrishnan Vijayan	[8]
26	Jingyan Zuo	[14]