| 2008 |
|---|
| 60 | EE | Djones Lettnin,
Pradeep Kumar Nalla,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel,
Tobias Kirsten,
Volker Schonknecht,
Stephan Reitemeyer:
Verification of Temporal Properties in Automotive Embedded Software.
DATE 2008: 164-169 |
| 2007 |
|---|
| 59 | EE | Thomas Kropf:
Software Bugs Seen from an Industrial Perspective or Can Formal Methods Help on Automotive Software Development?
CAV 2007: 3 |
| 58 | EE | Pradeep Kumar Nalla,
Jörg Behrend,
Prakash Mohan Peranandam,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Grid Based Fast Falsification For Bounded Property Checking.
FDL 2007: 299-304 |
| 57 | EE | Djones Lettnin,
Markus Winterholer,
Axel G. Braun,
Joachim Gerlach,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Coverage Driven Verification applied to Embedded Software.
ISVLSI 2007: 159-164 |
| 2006 |
|---|
| 56 | EE | Prakash Mohan Peranandam,
Pradeep Kumar Nalla,
Jürgen Ruf,
Roland J. Weiss,
Thomas Kropf,
Wolfgang Rosenstiel:
Fast falsification based on symbolic bounded property checking.
DAC 2006: 1077-1082 |
| 55 | EE | Pradeep Kumar Nalla,
Roland J. Weiss,
Prakash Mohan Peranandam,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Distributed Symbolic Bounded Property Checking.
Electr. Notes Theor. Comput. Sci. 135(2): 47-63 (2006) |
| 2005 |
|---|
| 54 | EE | Roland J. Weiss,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Efficient and Customizable Integration of Temporal Properties.
FDL 2005: 385-397 |
| 2004 |
|---|
| 53 | EE | Jürgen Ruf,
Roland J. Weiss,
Thomas Kropf,
Wolfgang Rosenstiel:
Modeling and Formal Verification of Production Automation Systems.
SoftSpez Final Report 2004: 541-566 |
| 2003 |
|---|
| 52 | EE | Jürgen Ruf,
Prakash Mohan Peranandam,
Thomas Kropf,
Wolfgang Rosenstiel:
Using Symbolic Simulation for Bounded Property Checking.
FDL 2003: 374-385 |
| 51 | EE | Jürgen Ruf,
Thomas Kropf:
Symbolic Verification and Analysis of Discrete Timed Systems.
Formal Methods in System Design 23(1): 67-108 (2003) |
| 2002 |
|---|
| 50 | EE | Jürgen Ruf,
Thomas Kropf:
Formal Data Analysis of Timed Finite State Systems.
ECRTS 2002: 257- |
| 49 | EE | Jürgen Ruf,
Thomas Kropf,
Jochen Klose:
A Visual Approach to Validating System Level Designs.
ISSS 2002: 186-191 |
| 2001 |
|---|
| 48 | EE | Jürgen Ruf,
Dirk W. Hoffmann,
Joachim Gerlach,
Thomas Kropf,
Wolfgang Rosenstiel,
Wolfgang Müller:
The simulation semantics of systemC.
DATE 2001: 64-70 |
| 47 | EE | Jürgen Ruf,
Dirk W. Hoffmann,
Thomas Kropf,
Wolfgang Rosenstiel:
Simulation-guided property checking based on a multi-valued AR-automata.
DATE 2001: 742-748 |
| 2000 |
|---|
| 46 | EE | Jürgen Ruf,
Thomas Kropf:
Analyzing Real-Time Systems.
DATE 2000: 243- |
| 45 | EE | Dirk W. Hoffmann,
Thomas Kropf:
Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits.
DATE 2000: 758 |
| 44 | EE | Dirk W. Hoffmann,
Thomas Kropf:
Can Automatic Design Error Correction be Applied to Large Circuits?
EUROMICRO 2000: 1114-1121 |
| 43 | EE | Dirk W. Hoffmann,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Simulation Meets Verification: Checking Temporal Properties in SystemC.
EUROMICRO 2000: 1435- |
| 42 | EE | Dirk W. Hoffmann,
Thomas Kropf:
Efficient Design Error Correction of Digital Circuits.
ICCD 2000: 465-472 |
| 1999 |
|---|
| 41 | | Laurence Pierre,
Thomas Kropf:
Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings
Springer 1999 |
| 40 | EE | Dirk W. Hoffmann,
Thomas Kropf:
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction.
CHARME 1999: 157-171 |
| 39 | EE | Jürgen Ruf,
Thomas Kropf:
Modleing and Checking Networks of Communicating Real-Time Process.
CHARME 1999: 265-279 |
| 38 | EE | Michaela Huhn,
Klaus Schneider,
Thomas Kropf,
George Logothetis:
Verifying Imprecisely Working Arithmetic Circuits.
DATE 1999: 65- |
| 37 | EE | Dirk W. Hoffmann,
Thomas Kropf:
Automatic Error Correction of Tri-State Circuits.
ICCD 1999: 51- |
| 36 | EE | Thomas Kropf:
Recent Advancements in Hardware Verification - How to Make Theorem Proving Fit for an Industrial Usage.
TPHOLs 1999: 1-4 |
| 1998 |
|---|
| 35 | EE | Ralf Reetz,
Klaus Schneider,
Thomas Kropf:
Formal Specification in VHDL for Hardware Verification.
DATE 1998: 257- |
| 34 | EE | Jürgen Ruf,
Thomas Kropf:
Using MTBDDs for Compostion and Model Checking of Real-Time Systems.
FMCAD 1998: 185-202 |
| 1997 |
|---|
| 33 | | Thomas Kropf:
Formal Hardware Verification - Methods and Systems in Comparison
Springer 1997 |
| 32 | | Jürgen Ruf,
Thomas Kropf:
Symbolic model checking for a discrete clocked temporal logic with intervals.
CHARME 1997: 146-163 |
| 31 | EE | Thomas Kropf,
Jürgen Ruf:
Using MTBDDs for discrete timed symbolic model checking.
ED&TC 1997: 182-187 |
| 30 | | Klaus Schneider,
Thomas Kropf:
The C@S System.
Formal Hardware Verification 1997: 248-329 |
| 29 | | Thomas Kropf:
Appendix: The Common Book Examples.
Formal Hardware Verification 1997: 330-367 |
| 28 | | Jürgen Ruf,
Thomas Kropf:
A New Algorithm for Discrete Timed Symbolic Model Checking.
HART 1997: 18-32 |
| 1996 |
|---|
| 27 | | Klaus Schneider,
Thomas Kropf:
A Unified Approach for Combining Different Formalisms for Hardware Verification.
FMCAD 1996: 202-217 |
| 1995 |
|---|
| 26 | EE | Ramayya Kumar,
Thomas Kropf,
Klaus Schneider:
Formal synthesis of circuits with a simple handshake protocol.
VLSI Design 1995: 255-259 |
| 25 | | Ralf Reetz,
Thomas Kropf:
A Flowgraph Semantics of VHDL: Toward a VHDL Verification Workbench in HOL.
Formal Methods in System Design 7(1/2): 73-99 (1995) |
| 24 | EE | Oliver F. Haberl,
Thomas Kropf:
HIST: A hierarchical self test methodology for chips, boards, and systems.
J. Electronic Testing 6(1): 85-106 (1995) |
| 1994 |
|---|
| 23 | | Ramayya Kumar,
Thomas Kropf:
Theorem Provers in Circuit Design - Theory, Practice and Experience, Second International Conference, TPCD '94, Bad Herrenalb, Germany, September 26-28, 1994, Proceedings
Springer 1994 |
| 22 | | Oliver F. Haberl,
Thomas Kropf:
Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface.
EDAC-ETC-EUROASIC 1994: 220-225 |
| 21 | | Jürgen Frößl,
Thomas Kropf:
A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation.
EDAC-ETC-EUROASIC 1994: 343-348 |
| 20 | | Klaus Schneider,
Thomas Kropf,
Ramayya Kumar:
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path.
EDAC-ETC-EUROASIC 1994: 648-652 |
| 19 | | Thomas Kropf:
Benchmark-Circuits for Hardware-Verification.
TPCD 1994: 1-12 |
| 18 | | Thomas Kropf,
Klaus Schneider,
Ramayya Kumar:
A Formal Framework for High Level Synthesis.
TPCD 1994: 223-238 |
| 17 | | Ralf Reetz,
Thomas Kropf:
Simplifying Deep Embedding: A Formalised Code Generator.
TPHOLs 1994: 378-390 |
| 16 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
Automating Verification by Functional Abstraction at the System Level.
TPHOLs 1994: 391-406 |
| 15 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
Accelerating Tableaux Proofs Using Compact Representations.
Formal Methods in System Design 5(1/2): 145-176 (1994) |
| 1993 |
|---|
| 14 | | Thomas Kropf,
Ramayya Kumar,
Klaus Schneider:
Embedding Hardware Verification Within a Commercial Design Framework.
CHARME 1993: 242-257 |
| 13 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
Hardware-Verification using First Order BDDs.
CHDL 1993: 45-62 |
| 12 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic.
HUG 1993: 213-226 |
| 11 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification.
HUG 1993: 385-398 |
| 10 | | Ramayya Kumar,
Klaus Schneider,
Thomas Kropf:
Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment.
Formal Methods in System Design 2(2): 165-223 (1993) |
| 1992 |
|---|
| 9 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
The FAUST - Prover.
CADE 1992: 766-770 |
| 8 | | Oliver F. Haberl,
Thomas Kropf:
HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test.
ITC 1992: 732-741 |
| 7 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
Modelling Generic Hardware Structures by Abstract Datatypes.
TPHOLs 1992: 165-175 |
| 6 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
Efficient Representation and Computation of Tableau Proofs.
TPHOLs 1992: 39-57 |
| 1991 |
|---|
| 5 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
Automating Most Parts of Hardware Proofs in HOL.
CAV 1991: 365-375 |
| 4 | | Thomas Kropf,
Hans-Joachim Wunderlich:
A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic.
ITC 1991: 57-66 |
| 3 | | Ramayya Kumar,
Thomas Kropf,
Klaus Schneider:
Integrating a First-Order Automatic Prover in the HOL Environment.
TPHOLs 1991: 170-176 |
| 2 | | Ramayya Kumar,
Thomas Kropf,
Klaus Schneider:
First Steps Towards Automating Hardware Proofs in HOL.
TPHOLs 1991: 190-193 |
| 1 | | Klaus Schneider,
Ramayya Kumar,
Thomas Kropf:
Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order Environment.
VLSI 1991: 81-90 |
