2006 |
49 | EE | Carlo Brandolese,
William Fornaciari,
Luigi Pomante,
Fabio Salice,
Donatella Sciuto:
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC.
IEEE Trans. Computers 55(5): 508-519 (2006) |
2005 |
48 | EE | Domenico Barretta,
William Fornaciari,
Mariagiovanna Sami,
Daniele Bagni:
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications.
DATE 2005: 748-749 |
2004 |
47 | EE | Luca Negri,
Domenico Barretta,
William Fornaciari:
Application-level power management in pervasive computing systems: a case study.
Conf. Computing Frontiers 2004: 78-88 |
46 | EE | Carlo Brandolese,
William Fornaciari,
Fabio Salice:
An area estimation methodology for FPGA based designs at systemc-level.
DAC 2004: 129-132 |
45 | EE | Carlo Brandolese,
William Fornaciari,
Fabio Salice,
Donatella Sciuto:
Analysis and Modeling of Energy Reducing Source Code Transformations.
DATE 2004: 306-311 |
44 | EE | Carlo Brandolese,
William Fornaciari,
Fabio Salice:
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures.
PATMOS 2004: 238-247 |
2003 |
43 | EE | William Fornaciari,
Fabio Salice,
Daniele Paolo Scarpazza:
Early estimation of the size of VHDL projects.
CODES+ISSS 2003: 207-212 |
42 | EE | William Fornaciari,
P. Micheli,
Fabio Salice,
L. Zampella:
A First Step Towards Hw/Sw Partitioning of UML Specifications.
DATE 2003: 10668-10673 |
41 | EE | Carlo Brandolese,
William Fornaciari,
Fabio Salice,
Donatella Sciuto:
Library Functions Timing Characterization for Source-Level Analysis.
DATE 2003: 11132-11133 |
40 | | Fabio Salice,
William Fornaciari,
Luigi Pomante,
Donatella Sciuto:
An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System.
FDL 2003: 669-680 |
39 | | Fabio Salice,
William Fornaciari,
Luca Del Vecchio,
Luigi Pomante:
Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures.
SAC 2003: 661-665 |
2002 |
38 | EE | Donatella Sciuto,
Fabio Salice,
Luigi Pomante,
William Fornaciari:
Metrics for design space exploration of heterogeneous multiprocessor embedded systems.
CODES 2002: 55-60 |
37 | EE | Domenico Barretta,
William Fornaciari,
Mariagiovanna Sami,
Danilo Pau:
SIMD Extension to VLIW Multicluster Processors for Embedded Applications.
ICCD 2002: 523-526 |
36 | EE | William Fornaciari,
Vito Trianni,
Carlo Brandolese,
Donatella Sciuto,
Fabio Salice,
Giovanni Beltrame:
Modeling Assembly Instruction Timing in Superscalar Architectures.
ISSS 2002: 132-137 |
35 | EE | Carlo Brandolese,
Fabio Salice,
William Fornaciari,
Donatella Sciuto:
Static power modeling of 32-bit microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1306-1316 (2002) |
34 | EE | Carlo Brandolese,
William Fornaciari,
Fabio Salice,
Donatella Sciuto:
The Impact of Source Code Transformations on Software Power and Energy Consumption.
Journal of Circuits, Systems, and Computers 11(5): 477-502 (2002) |
2001 |
33 | EE | William Fornaciari,
Donatella Sciuto,
Cristina Silvano,
Vittorio Zaccaria:
A design framework to efficiently explore energy-delay tradeoffs.
CODES 2001: 260-265 |
32 | EE | William Fornaciari,
Fabio Salice,
Umberto Bondi,
Edi Magini:
Development cost and size estimation starting from high-level specifications.
CODES 2001: 86-91 |
31 | EE | Carlo Brandolese,
William Fornaciari,
Fabio Salice,
Donatella Sciuto:
Source-level execution time estimation of C programs.
CODES 2001: 98-103 |
30 | EE | Giovanni Beltrame,
Carlo Brandolese,
William Fornaciari,
Fabio Salice,
Donatella Sciuto,
Vito Trianni:
An Assembly-Level Execution-Time Model for Pipelined Architectures.
ICCAD 2001: 195-200 |
29 | EE | Cesare Alippi,
William Fornaciari,
Laura Pozzi,
Mariagiovanna Sami:
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.
IEEE International Workshop on Rapid System Prototyping 2001: 50-57 |
28 | EE | William Fornaciari,
Donatella Sciuto,
Cristina Silvano,
Vittorio Zaccaria:
Fast system-level exploration of memory architectures driven by energy-delay metrics.
ISCAS (4) 2001: 502-505 |
27 | | Giovanni Beltrame,
Carlo Brandolese,
William Fornaciari,
Fabio Salice,
Donatella Sciuto,
Vito Trianni:
Dynamic modeling of inter-instruction effects for execution time estimation.
ISSS 2001: 136-141 |
26 | EE | William Fornaciari,
Vincenzo Piuri,
Andrea Prestileo,
Vittorio Zaccaria:
An Agent-Based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems.
MATA 2001: 153-162 |
2000 |
25 | EE | Carlo Brandolese,
William Fornaciari,
Fabio Salice,
Donatella Sciuto:
Energy estimation for 32-bit microprocessors.
CODES 2000: 24-28 |
24 | EE | William Fornaciari,
M. Polentarutti,
Donatella Sciuto,
Cristina Silvano:
Power optimization of system-level address buses based on software profiling.
CODES 2000: 29-33 |
23 | EE | Carlo Brandolese,
William Fornaciari,
Fabio Salice,
Donatella Sciuto:
An instruction-level functionally-based energy estimation model for 32-bits microprocessors.
DAC 2000: 346-351 |
22 | EE | Cesare Alippi,
William Fornaciari,
Laura Pozzi,
Mariagiovanna Sami:
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract).
FPGA 2000: 218 |
21 | EE | William Fornaciari,
Vincenzo Piuri,
Luigi Ripamonti:
Virtualization of FPGA via segmentation (poster abstract).
FPGA 2000: 222 |
20 | EE | Carlo Brandolese,
William Fornaciari,
Luigi Pomante,
Fabio Salice,
Donatella Sciuto:
A Multi-Level Strategy for Software Power Estimation.
ISSS 2000: 187-192 |
19 | EE | Alberto Allara,
Massimo Bombana,
William Fornaciari,
Fabio Salice:
A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller.
IEEE Design & Test of Computers 17(2): 60-72 (2000) |
1999 |
18 | EE | William Fornaciari,
Donatella Sciuto:
HW/SW Co-design of Embedded Systems.
Ada-Europe 1999: 344-355 |
17 | EE | William Fornaciari,
Donatella Sciuto,
Cristina Silvano:
Power estimation for architectural exploration of HW/SW communication on system-level buses.
CODES 1999: 152-156 |
16 | EE | William Fornaciari,
Donatella Sciuto,
Cristina Silvano:
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems.
DATE 1999: 762-763 |
15 | EE | Cesare Alippi,
William Fornaciari,
Laura Pozzi,
Mariagiovanna Sami:
A DAG-Based Design Approach for Reconfigurable VLIW Processors.
DATE 1999: 778-779 |
14 | EE | William Fornaciari,
Donatella Sciuto,
Cristina Silvano:
Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study.
ICCD 1999: 131- |
1998 |
13 | EE | Alberto Allara,
William Fornaciari,
Fabio Salice,
Donatella Sciuto:
A Model for System-Level Timed Analysis and Profiling.
DATE 1998: 204-210 |
12 | | William Fornaciari,
Vincenzo Piuri:
Virtual FPGAs: Some Steps Behind the Physical Barriers.
IPPS/SPDP Workshops 1998: 7-12 |
11 | EE | Cristiana Bolchini,
William Fornaciari,
Fabio Salice,
Donatella Sciuto:
Concurrent Error Detection at Architectural Level.
ISSS 1998: 72-75 |
10 | EE | William Fornaciari,
P. Gubian,
Donatella Sciuto,
Cristina Silvano:
Power estimation of embedded systems: a hardware/software codesign approach.
IEEE Trans. VLSI Syst. 6(2): 266-275 (1998) |
1997 |
9 | EE | Alberto Allara,
S. Filipponi,
Fabio Salice,
William Fornaciari,
Donatella Sciuto:
A Flexible Model for Evaluating the Behavior of Hardware/Software Systems.
CODES 1997: 109-114 |
8 | | Alberto Allara,
S. Filipponi,
William Fornaciari,
Fabio Salice,
Donatella Sciuto:
Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation.
ICCD 1997: 400-405 |
7 | | William Fornaciari,
Donatella Sciuto:
A Two-Level Cosimulation Environment.
IEEE Computer 30(6): 109-111 (1997) |
1996 |
6 | EE | Alessandro Balboni,
William Fornaciari,
Donatella Sciuto:
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow.
CODES 1996: 62-69 |
5 | EE | Alessandro Balboni,
William Fornaciari,
M. Vincenzi,
Donatella Sciuto:
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems.
ISSS 1996: 77-82 |
1995 |
4 | EE | William Fornaciari,
Fabio Salice:
A new architecture for the automatic design of custom digital neural network.
IEEE Trans. VLSI Syst. 3(4): 502-506 (1995) |
1994 |
3 | EE | Stefano Antoniazzi,
Alessandro Balboni,
William Fornaciari,
Donatella Sciuto:
A methodology for control-dominated systems codesign.
CODES 1994: 2-9 |
2 | EE | Donatella Sciuto,
Stefano Antoniazzi,
Alessandro Balboni,
William Fornaciari:
The role of VHDL within the TOSCA hardware/software codesign framework.
EURO-DAC 1994: 612-617 |
1 | | Stefano Antoniazzi,
Alessandro Balboni,
William Fornaciari,
Donatella Sciuto:
HW/SW Codesign for Embedded Telecom Systems.
ICCD 1994: 278-281 |