Edwin Naroska

2008
20	EE	Todor Dimitrov, Josef Pauli, Edwin Naroska, Christian Ressel: Structured Learning of Component Dependencies in AmI Systems. IAT 2008: 118-124
2007
19	EE	Todor Dimitrov, Josef Pauli, Edwin Naroska: A probabilistic reasoning framework for smart homes. MPAC 2007: 1-6
2006
18	EE	Jörg Platte, Edwin Naroska, Kai Grundmann: A Cache Design for a Security Architecture for Microprocessors (SAM). ARCS 2006: 435-449
17	EE	Jörg Platte, Raúl Durán Díaz, Edwin Naroska: A New Encryption and Hashing Scheme for the Security Architecture for Microprocessors. Communications and Multimedia Security 2006: 120-129
16	EE	Jörg Platte, Raúl Durán Díaz, Edwin Naroska: An Operating System Design for the Security Architecture for Microprocessors. ICICS 2006: 174-189
15	EE	Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen: Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. ISPD 2006: 114-119
14	EE	Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn: Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing. IEEE Trans. VLSI Syst. 14(4): 421-425 (2006)
2005
13	EE	Jörg Platte, Edwin Naroska: A combined hardware and software architecture for secure computing. Conf. Computing Frontiers 2005: 280-288
12		Uwe Schwiegelshohn, Edwin Naroska: Verlustleistungsarme Fehlerschutzprotokolle basierend auf punktierten Low Density Parity Check Codes (LDPC). GI Jahrestagung (1) 2005: 461
11	EE	Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn: Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design. IPDPS 2005
10	EE	Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn: An efficient algorithm for simultaneous wire permutation, inversion, and spacing. ISCAS (1) 2005: 109-112
9	EE	Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai: Bipartitioning and encoding in low-power pipelined circuits. ACM Trans. Design Autom. Electr. Syst. 10(1): 24-32 (2005)
2003
8	EE	Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu: On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms. ISCAS (5) 2003: 277-280
2002
7	EE	Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai: Energy analysis of bipartition architecture for pipelined circuits. APCCAS (2) 2002: 7-11
6	EE	Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai: Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. ICCD 2002: 327-
5	EE	Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn: ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. IEEE Trans. VLSI Syst. 10(6): 942-949 (2002)
4	EE	Edwin Naroska, Uwe Schwiegelshohn: On an on-line scheduling problem for parallel jobs. Inf. Process. Lett. 81(6): 297-304 (2002)
2000
3	EE	Edwin Naroska, Rung-Ji Shang, Feipei Lai, Uwe Schwiegelshohn: Hybrid Parallel Circuit Simulation Approaches. IEEE PACT 2000: 261-270
1998
2	EE	Edwin Naroska: Parallel VHDL Simulation. DATE 1998: 159-
1996
1		Edwin Naroska, Uwe Schwiegelshohn: A New Scheduling Method for Parallel Discrete-Event Simulation. Euro-Par, Vol. II 1996: 582-593

Coauthor Index

1	Yen-Jen Chang	[5] [7]
2	Chun-Chih Chen	[15]
3	Raúl Durán Díaz	[16] [17]
4	Todor Dimitrov	[19] [20]
5	Kai Grundmann	[18]
6	Chia-Lin Ho	[6] [7]
7	Feipei Lai	[3] [5] [6] [7] [8] [9]
8	Le-Chin Liu	[8]
9	Josef Pauli	[19] [20]
10	Jörg Platte	[13] [16] [17] [18]
11	Christian Ressel	[20]
12	Shanq-Jang Ruan	[5] [6] [7] [8] [9] [10] [11] [14] [15]
13	Uwe Schwiegelshohn	[1] [3] [4] [5] [8] [10] [11] [12] [14]
14	Rung-Ji Shang	[3]
15	Kun-Lin Tsai	[9]

Colors in the list of coauthors