| 2008 |
| 31 | EE | Man Yan Kong,
J. M. Pierre Langlois,
Dhamin Al-Khalili:
Efficient FPGA implementation of complex multipliers using the logarithmic number system.
ISCAS 2008: 3154-3157 |
| 2007 |
| 30 | EE | Shuli Gao,
Noureddine Chabini,
Dhamin Al-Khalili,
J. M. Pierre Langlois:
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers.
ASAP 2007: 18-23 |
| 2006 |
| 29 | EE | Donald B. Shaw,
Dhamin Al-Khalili,
Come Rozon:
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries.
Integration 39(4): 382-406 (2006) |
| 2005 |
| 28 | | Hussam Al-Hertani,
Dhamin Al-Khalili,
Come Rozon:
Leakage power dissipation in UDSM logic gates.
Circuits, Signals, and Systems 2005: 132-136 |
| 27 | EE | Haydar Saaied,
Dhamin Al-Khalili,
Asim J. Al-Khalili,
Mohamed Nekili:
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1637-1643 (2005) |
| 26 | EE | Adnan Kabbani,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
Delay analysis of CMOS gates using modified logical effort model.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 937-947 (2005) |
| 2003 |
| 25 | EE | Donald B. Shaw,
Dhamin Al-Khalili,
Come Rozon:
IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs.
IEEE Trans. Computers 52(10): 1285-1297 (2003) |
| 24 | EE | Adnan Kabbani,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
Technology-portable analytical model for DSM CMOS inverter transition-time estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1177-1187 (2003) |
| 2002 |
| 23 | EE | J. M. Pierre Langlois,
Dhamin Al-Khalili:
A low power direct digital frequency synthesizer with 60 dBc spectral purity.
ACM Great Lakes Symposium on VLSI 2002: 166-171 |
| 22 | EE | J. M. Pierre Langlois,
Dhamin Al-Khalili:
Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity.
ISCAS (5) 2002: 361-364 |
| 21 | EE | Haydar Saaied,
Dhamin Al-Khalili,
Asim J. Al-Khalili,
Mohamed Nekili:
Quadratic deferred-merge embedding algorithm for zero skew clock distribution network.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 119-125 |
| 20 | EE | Donald B. Shaw,
Dhamin Al-Khalili,
Come Rozon:
Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models.
Integration 32(1-2): 77-97 (2002) |
| 19 | EE | J. M. Pierre Langlois,
Dhamin Al-Khalili,
Robert J. Inkol:
Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation.
VLSI Signal Processing 32(3): 237-254 (2002) |
| 2001 |
| 18 | EE | Donald B. Shaw,
Dhamin Al-Khalili,
Come Rozon:
Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs.
ICCAD 2001: 531-536 |
| 17 | EE | Donald B. Shaw,
Dhamin Al-Khalili,
Come Rozon:
Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation.
ISCAS (5) 2001: 263-266 |
| 16 | EE | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili,
S. Y. A. Shah:
A Low Power Approach to Floating Point Adder Design for DSP Applications.
VLSI Signal Processing 27(3): 195-213 (2001) |
| 1999 |
| 15 | EE | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
Power implications of precision limited arithmetic in floating point FIR filters.
ISCAS (1) 1999: 165-168 |
| 14 | | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
An IEEE Compliant Floating Point MAF.
VLSI 1999: 149-160 |
| 13 | EE | Michael Gallant,
Dhamin Al-Khalili:
Synthesis of low-power CMOS circuits using hybrid topologies.
Integration 27(2): 143-163 (1999) |
| 1998 |
| 12 | EE | Jason Coppens,
Dhamin Al-Khalili,
Come Rozon:
VHDL Modelling and Analysis of Fault Secure Systems.
DATE 1998: 148-152 |
| 11 | EE | Dhamin Al-Khalili,
Saman Adham,
Come Rozon,
Moazzem Hossain,
D. Racz:
Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits.
DFT 1998: 84-92 |
| 10 | EE | R. V. K. Pillai,
Asim J. Al-Khalili,
Dhamin Al-Khalili:
A Low Power Floating Point Accumulator.
VLSI Design 1998: 330- |
| 1997 |
| 9 | | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
A Low Power Approach to Floating Point Adder Design.
ICCD 1997: 178-185 |
| 8 | EE | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition.
ISLPED 1997: 235-238 |
| 1996 |
| 7 | EE | R. V. K. Pillai,
Dhamin Al-Khalili,
Asim J. Al-Khalili:
Energy delay analysis of partial product reduction methods for parallel multiplier implementation.
ISLPED 1996: 201-204 |
| 1995 |
| 6 | EE | Michael Ogbonna Esonu,
Asim J. Al-Khalili,
Salim Hariri,
Dhamin Al-Khalili:
Design techniques for fault-tolerant systolic arrays.
VLSI Signal Processing 11(1-2): 151-168 (1995) |
| 1994 |
| 5 | EE | T. C. Davies,
Dhamin Al-Khalili,
V. Szwarc:
A floating-point systolic array processing element with serial communication and built-in self-test.
VLSI Signal Processing 8(3): 241-251 (1994) |
| 1993 |
| 4 | | Michael Ogbonna Esonu,
Dhamin Al-Khalili,
Come Rozon:
Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits.
ISCAS 1993: 1714-1717 |
| 1992 |
| 3 | EE | Dhamin Al-Khalili,
Come Rozon,
B. Stewart:
Testability analysis and fault modeling of BiCMOS circuits.
J. Electronic Testing 3(3): 207-217 (1992) |
| 1990 |
| 2 | EE | Asim J. Al-Khalili,
Yong Zhu,
Dhamin Al-Khalili:
A module generator for optimized CMOS buffers.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 1028-1046 (1990) |
| 1989 |
| 1 | EE | Asim J. Al-Khalili,
Yong Zhu,
Dhamin Al-Khalili:
A Module Generator for Optimized CMOS Buffers.
DAC 1989: 245-250 |