| 2008 |
|---|
| 15 | EE | Felipe Machado,
Teresa Riesgo,
Yago Torroja:
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level.
PATMOS 2008: 399-408 |
| 2007 |
|---|
| 14 | EE | Yaseer A. Durrani,
Ana Abril,
Teresa Riesgo:
Efficient Power Macromodeling Technique for IP-Based Digital System.
ISCAS 2007: 1145-1148 |
| 13 | EE | Yana Esteves Krasteva,
Eduardo de la Torre,
Teresa Riesgo:
Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management.
ISCAS 2007: 873-876 |
| 2006 |
|---|
| 12 | EE | Yana Esteves Krasteva,
Eduardo de la Torre,
Teresa Riesgo,
Didier Joly:
Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems.
FPL 2006: 1-4 |
| 11 | | Yaseer A. Durrani,
Teresa Riesgo,
Felipe Machado:
Power estimation for register transfer level by genetic algorithm.
ICINCO-RA 2006: 527-530 |
| 10 | EE | Felipe Machado,
Teresa Riesgo,
Yago Torroja:
A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits.
PATMOS 2006: 645-657 |
| 9 | | Yaseer A. Durrani,
Teresa Riesgo:
Power Macromodeling for High Level Power Estimation.
ReCoSoC 2006: 232-236 |
| 8 | | Yana Esteves Krasteva,
Eduardo de la Torre,
Teresa Riesgo:
Partial Reconfiguration for Core Reallocation and Flexible Communications.
ReCoSoC 2006: 91-97 |
| 7 | EE | José Bravo,
Xavier Alamán,
Teresa Riesgo:
Ubiquitous Computing and Ambient Intelligence: New Challenges for Computing.
J. UCS 12(3): 233-235 (2006) |
| 6 | EE | Jorge Portilla,
Angel de Castro,
Eduardo de la Torre,
Teresa Riesgo:
A Modular Architecture for Nodes in Wireless Sensor Networks.
J. UCS 12(3): 328-339 (2006) |
| 2005 |
|---|
| 5 | | Yana Esteves Krasteva,
Ana B. Jimeno,
Eduardo de la Torre,
Teresa Riesgo:
Flexible Core Reallocation for Virtex II Structures.
ERSA 2005: 189-195 |
| 4 | EE | Yana Esteves Krasteva,
Ana B. Jimeno,
Eduardo de la Torre,
Teresa Riesgo:
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs.
IEEE International Workshop on Rapid System Prototyping 2005: 77-83 |
| 2004 |
|---|
| 3 | EE | M. G. Valderas,
Eduardo de la Torre,
F. Ariza,
Teresa Riesgo:
Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion.
FPL 2004: 1057-1061 |
| 2000 |
|---|
| 2 | EE | Eduardo de la Torre,
Teresa Riesgo,
J. Uceda,
E. Macip,
M. Rizzi:
Highly Configurable Control Boards: A Tool and a Design Experience.
IEEE International Workshop on Rapid System Prototyping 2000: 174- |
| 1998 |
|---|
| 1 | EE | Teresa Riesgo,
Yago Torroja,
Eduardo de la Torre,
J. Uceda:
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models.
DATE 1998: 955-956 |
