Gopal Vija
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1998
1
EE
Satyamurthy Pullela
,
Rajendran Panda
,
Abhijit Dharchoudhury
, Gopal Vija: CMOS Combinational Circuit Sizing by Stage-wise Tapering.
DATE 1998
: 985-988
Coauthor
Index
1
Abhijit Dharchoudhury
[
1
]
2
Rajendran Panda
[
1
]
3
Satyamurthy Pullela
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)