| 2000 |
|---|
| 4 | EE | Charles H. Ouyang,
Hans T. Heineken,
Jitendra Khare,
Saghir A. Shaikh,
M. d'Abreu:
Maximizing Wafer Productivity Through Layout Optimization.
VLSI Design 2000: 192-197 |
| 1999 |
|---|
| 3 | EE | Witold A. Pleskacz,
Charles H. Ouyang,
Wojciech Maly:
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 151-162 (1999) |
| 1998 |
|---|
| 2 | EE | Wojciech Maly,
Pranab K. Nag,
Charles H. Ouyang,
Hans T. Heineken,
Jitendra Khare,
P. Simon:
Design-Manufacturing Interface: Part II - Applications.
DATE 1998: 557-562 |
| 1997 |
|---|
| 1 | EE | Hans T. Heineken,
Jitendra Khare,
Wojciech Maly,
Pranab K. Nag,
Charles H. Ouyang,
Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface.
DAC 1997: 321-326 |
