| 2000 |
|---|
| 10 | EE | Preetham Lakshmikanthan,
Sriram Govindarajan,
Vinoo Srinivasan,
Ranga Vemuri:
Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints.
IPDPS Workshops 2000: 924-931 |
| 9 | EE | Sriram Govindarajan,
Vinoo Srinivasan,
Preetham Lakshmikanthan,
Ranga Vemuri:
A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures.
VLSI Design 2000: 212-219 |
| 1999 |
|---|
| 8 | EE | Vinoo Srinivasan,
Ranga Vemuri:
Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures.
FCCM 1999: 272- |
| 7 | EE | Vinoo Srinivasan,
Ranga Vemuri:
Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures.
FPGA 1999: 253 |
| 6 | | Vinoo Srinivasan,
Shankar Radhakrishnan,
Ranga Vemuri,
Jeffrey Walrath:
Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures.
IPPS/SPDP Workshops 1999: 588-596 |
| 1998 |
|---|
| 5 | EE | Vinoo Srinivasan,
Shankar Radhakrishnan,
Ranga Vemuri:
Hardware Software Partitioning with Integrated Hardware Design Space Exploration.
DATE 1998: 28-35 |
| 4 | EE | Sriram Govindarajan,
Iyad Ouaiss,
Meenakshi Kaul,
Vinoo Srinivasan,
Ranga Vemuri:
An Effective Design System for Dynamically Reconfigurable Architectures.
FCCM 1998: 312-313 |
| 3 | | Iyad Ouaiss,
Sriram Govindarajan,
Vinoo Srinivasan,
Meenakshi Kaul,
Ranga Vemuri:
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures.
IPPS/SPDP Workshops 1998: 31-36 |
| 2 | EE | Vinoo Srinivasan,
Ranga Vemuri:
A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining.
VLSI Design 1998: 435-441 |
| 1996 |
|---|
| 1 | EE | Naren Narasimhan,
Vinoo Srinivasan,
Madhavi Vootukuru,
Jeffrey Walrath,
Sriram Govindarajan,
Ranga Vemuri:
Rapid Prototyping of Reconfigurable Coprocessors.
ASAP 1996: 303-312 |
