| 2001 |
| 12 | | Qin Zhao,
Twan Basten,
Bart Mesman,
C. A. J. van Eijk,
Jochen A. G. Jess:
Static resource models of instruction sets.
ISSS 2001: 159-164 |
| 2000 |
| 11 | EE | Luiz C. V. dos Santos,
Marc J. M. Heijligers,
C. A. J. van Eijk,
J. Van Eijnhoven,
Jochen A. G. Jess:
A code-motion pruning technique for global scheduling.
ACM Trans. Design Autom. Electr. Syst. 5(1): 1-38 (2000) |
| 10 | EE | C. A. J. van Eijk:
Sequential equivalence checking based on structural similarities.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 814-819 (2000) |
| 1999 |
| 9 | EE | C. A. J. van Eijk,
E. T. A. F. Jacobs,
Bart Mesman,
Adwin H. Timmer:
Identification and Exploitation of Symmetries in DSP Algorithms.
DATE 1999: 602-608 |
| 1998 |
| 8 | EE | C. A. J. van Eijk:
Sequential Equivalence Checking without State Space Traversal.
DATE 1998: 618-623 |
| 7 | EE | J. W. J. M. Rutten,
Michel R. C. M. Berkelaar,
C. A. J. van Eijk,
M. A. J. Kolsteren:
An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization.
DATE 1998: 749-754 |
| 6 | EE | R. X. T. Nijssen,
C. A. J. van Eijk:
GreyHound: A methodology for utilizing datapath regularity in standard design flows.
Integration 25(2): 111-135 (1998) |
| 1997 |
| 5 | EE | R. X. T. Nijssen,
C. A. J. van Eijk:
Regular layout generation of logically optimized datapaths.
ISPD 1997: 42-47 |
| 4 | EE | C. A. J. van Eijk:
A BDD-based verification method for large synthesized circuits.
Integration 23(2): 131-149 (1997) |
| 1996 |
| 3 | EE | Harm Arts,
Michel R. C. M. Berkelaar,
C. A. J. van Eijk:
Polarized observability don't cares.
ICCAD 1996: 626-631 |
| 2 | EE | Luiz C. V. dos Santos,
Marc J. M. Heijligers,
C. A. J. van Eijk,
Jos T. J. van Eijndhoven,
Jochen A. G. Jess:
A Constructive Method for Exploiting Code Motion.
ISSS 1996: 51-56 |
| 1994 |
| 1 | | C. A. J. van Eijk,
Geert Janssen:
Exploiting Structural Similarities in a BDD-Based Verification Method.
TPCD 1994: 110-125 |