Ganesh Lakshminarayana

2006
47	EE	Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana: The LOTTERYBUS on-chip communication architecture. IEEE Trans. VLSI Syst. 14(6): 596-608 (2006)
2005
46	EE	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: Memory binding for performance optimization of control-flow intensive behavioral descriptions. IEEE Trans. VLSI Syst. 13(5): 513-524 (2005)
45	EE	Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input space-adaptive optimization for embedded-software synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1677-1693 (2005)
2004
44	EE	Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input space adaptive design: a high-level methodology for optimizing energy and performance. IEEE Trans. VLSI Syst. 12(6): 590-602 (2004)
43	EE	Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey: Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 33-49 (2004)
42	EE	Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey: Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 620-636 (2004)
2003
41	EE	Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Analysis of power dissipation in embedded systems using real-time operating systems. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 615-627 (2003)
2002
40	EE	Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input Space Adaptive Embedded Software Synthesis. VLSI Design 2002: 711-718
39	EE	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: High-level test compaction techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 827-841 (2002)
38	EE	Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: High-level energy macromodeling of embedded software. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1037-1050 (2002)
2001
37	EE	Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana: LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. DAC 2001: 15-20
36	EE	Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: High-level Software Energy Macro-modeling. DAC 2001: 605-610
35	EE	Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha: Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. DAC 2001: 738-743
34	EE	Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana: Transient Power Management Through High Level Synthesis. ICCAD 2001: 545-552
33	EE	Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar: Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design 2001: 235-241
32	EE	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. VLSI Syst. 9(6): 824-832 (2001)
31	EE	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: Testing of core-based systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 426-439 (2001)
2000
30	EE	Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Power analysis of embedded operating systems. DAC 2000: 312-315
29	EE	Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey: Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC 2000: 513-518
28		Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: : Reducing test application time in high-level test generation. ITC 2000: 829-838
27	EE	Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana: High-Level Synthesis with Variable-Latency Components. VLSI Design 2000: 220-227
26	EE	Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. IEEE Trans. Computers 49(9): 865-885 (2000)
25	EE	Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana: Integrating variable-latency components into high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1105-1117 (2000)
24	EE	Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 308-324 (2000)
23	EE	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 894-906 (2000)
1999
22	EE	Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey: Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC 1999: 56-61
21	EE	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: A framework for testing core-based systems-on-a-chip. ICCAD 1999: 385-390
20	EE	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: Memory binding for performance optimization of control-flow intensive behaviors. ICCAD 1999: 482-488
19	EE	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS 1999: 398-406
18	EE	Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey: Power management in high-level synthesis. IEEE Trans. VLSI Syst. 7(1): 7-15 (1999)
17	EE	Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha: COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. IEEE Trans. VLSI Syst. 7(1): 92-104 (1999)
16	EE	Ganesh Lakshminarayana, Niraj K. Jha: FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1577-1594 (1999)
15	EE	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: High-level synthesis of low-power control-flow intensive circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1715-1729 (1999)
14	EE	Ganesh Lakshminarayana, Niraj K. Jha: High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 265-281 (1999)
13	EE	Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha: Wavesched: a novel scheduling technique for control-flow intensive designs. IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 505-523 (1999)
1998
12	EE	Ganesh Lakshminarayana, Niraj K. Jha: FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions. DAC 1998: 102-107
11	EE	Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. DAC 1998: 108-113
10	EE	Ganesh Lakshminarayana, Niraj K. Jha: Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. DAC 1998: 439-444
9	EE	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. DATE 1998: 848-854
8	EE	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. ICCAD 1998: 577-584
7	EE	Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey: Transforming control-flow intensive designs to facilitate power management. ICCAD 1998: 657-664
6	EE	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha: Fast high-level power estimation for control-flow intensive design. ISLPED 1998: 299-304
5	EE	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO: regular expression based high-level testability analysis and optimization. ITC 1998: 331-340
4		Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey: A Power Management Methodology for High-Level Synthesis. VLSI Design 1998: 24-19
1997
3	EE	Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha: COSYN: Hardware-Software Co-Synthesis of Embedded Systems. DAC 1997: 703-708
2	EE	Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha: Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. ICCAD 1997: 244-250
1996
1		Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha: Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. FTCS 1996: 336-345

Coauthor Index

1	Srimat T. Chakradhar	[33]
2	Bharat P. Dave	[3] [17]
3	Sujit Dey	[4] [7] [18] [22] [29] [42] [43]
4	Robert P. Dick	[30] [41]
5	Michael S. Hsiao	[33]
6	Niraj K. Jha	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [26] [28] [30] [31] [32] [35] [36] [38] [39] [40] [41] [43] [44] [45] [46]
7	Kamal S. Khouri	[2] [6] [9] [13] [15] [20] [22] [43] [46]
8	Kanishka Lahiri	[29] [37] [42] [47]
9	Nachiketh R. Potlapally	[33]
10	Anand Raghunathan	[1] [4] [7] [11] [18] [22] [24] [26] [29] [30] [33] [34] [35] [36] [37] [38] [40] [41] [42] [43] [44] [45] [47]
11	Vijay Raghunathan	[25] [27] [34]
12	Srivaths Ravi	[5] [8] [19] [21] [23] [25] [27] [28] [31] [32] [34] [39]
13	Tat Kee Tan	[36] [38]
14	Weidong Wang	[35] [40] [44] [45]