| 2002 |
|---|
| 15 | EE | Pinhong Chen,
Yuji Kukimoto,
Kurt Keutzer:
Refining switching window by time slots for crosstalk noise calculation.
ICCAD 2002: 583-586 |
| 14 | EE | Pinhong Chen,
Yuji Kukimoto,
Chin-Chi Teng,
Kurt Keutzer:
On convergence of switching windows computation in presence of crosstalk noise.
ISPD 2002: 84-89 |
| 1999 |
|---|
| 13 | EE | Yuji Kukimoto,
Robert K. Brayton:
Timing-safe false path removal for combinational modules.
ICCAD 1999: 544-550 |
| 1998 |
|---|
| 12 | EE | Yuji Kukimoto,
Robert K. Brayton,
Prashant Sawkar:
Delay-Optimal Technology Mapping by DAG Covering.
DAC 1998: 348-351 |
| 11 | EE | Yuji Kukimoto,
Robert K. Brayton:
Hierarchical Functional Timing Analysis.
DAC 1998: 580-585 |
| 10 | EE | Evguenii I. Goldberg,
Yuji Kukimoto,
Robert K. Brayton:
Combinational Verification based on High-Level Functional Specifications.
DATE 1998: 803- |
| 1997 |
|---|
| 9 | EE | Yuji Kukimoto,
Robert K. Brayton:
Exact Required Time Analysis via False Path Detection.
DAC 1997: 220-225 |
| 8 | EE | Yuji Kukimoto,
Wilsin Gosti,
Alexander Saldanha,
Robert K. Brayton:
Approximate timing analysis of combinational circuits under the XBD0 model.
ICCAD 1997: 176-181 |
| 1996 |
|---|
| 7 | | Robert K. Brayton,
Gary D. Hachtel,
Alberto L. Sangiovanni-Vincentelli,
Fabio Somenzi,
Adnan Aziz,
Szu-Tsung Cheng,
Stephen A. Edwards,
Sunil P. Khatri,
Yuji Kukimoto,
Abelardo Pardo,
Shaz Qadeer,
Rajeev K. Ranjan,
Shaker Sarwary,
Thomas R. Shiple,
Gitanjali Swamy,
Tiziano Villa:
VIS: A System for Verification and Synthesis.
CAV 1996: 428-432 |
| 6 | | Robert K. Brayton,
Gary D. Hachtel,
Alberto L. Sangiovanni-Vincentelli,
Fabio Somenzi,
Adnan Aziz,
Szu-Tsung Cheng,
Stephen A. Edwards,
Sunil P. Khatri,
Yuji Kukimoto,
Abelardo Pardo,
Shaz Qadeer,
Rajeev K. Ranjan,
Shaker Sarwary,
Thomas R. Shiple,
Gitanjali Swamy,
Tiziano Villa:
VIS.
FMCAD 1996: 248-256 |
| 1994 |
|---|
| 5 | EE | Yuji Kukimoto,
Masahiro Fujita,
Robert K. Brayton:
A redesign technique for combinational circuits based on gate reconnections.
ICCAD 1994: 632-637 |
| 1992 |
|---|
| 4 | | Masahiro Fujita,
Yuji Kukimoto:
Patching Method for Lookup-Table Type FPLs.
FPL 1992: 61-70 |
| 3 | EE | Yuji Kukimoto,
Masahiro Fujita:
Rectification method for lookup-table type FPGA's.
ICCAD 1992: 54-61 |
| 1991 |
|---|
| 2 | | Masahiro Fujita,
Yutaka Tamiya,
Yuji Kukimoto,
Kuang-Chien Chen:
Application of Boolean Unification to Combinational Logic Synthesis.
ICCAD 1991: 510-513 |
| 1990 |
|---|
| 1 | | Hiroshi Nakamura,
Yuji Kukimoto,
Masahiro Fujita,
Hidehiko Tanaka:
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio.
CAV 1990: 76-85 |
