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Mario Kovac

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1998
6EEDavor Runje, Mario Kovac: Universal Strong Encryption FPGA Core Implementation. DATE 1998: 923-924
1995
5EEMario Kovac, N. Ranganathan: JAGUAR: a high speed VLSI chip for JPEG image compression standard. VLSI Design 1995: 220-224
1994
4 Mario Kovac, N. Ranganathan: ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. VLSI Design 1994: 291-296
1993
3 Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. VLSI Design 1993: 25-30
2EEMario Kovac, N. Ranganathan, M. Varanasi: SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm. IEEE Trans. VLSI Syst. 1(1): 22-30 (1993)
1992
1 Mario Kovac, N. Ranganathan, M. Varanasi: A Systolic Algorithm and Architecture for Galois Field Arithmetic. IPPS 1992: 283-288

Coauthor Index

1N. Ranganathan (Nagarajan Ranganathan) [1] [2] [3] [4] [5]
2Davor Runje [6]
3M. Varanasi [1] [2] [3]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)