Mario Kovac

1998
6	EE	Davor Runje, Mario Kovac: Universal Strong Encryption FPGA Core Implementation. DATE 1998: 923-924
1995
5	EE	Mario Kovac, N. Ranganathan: JAGUAR: a high speed VLSI chip for JPEG image compression standard. VLSI Design 1995: 220-224
1994
4		Mario Kovac, N. Ranganathan: ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. VLSI Design 1994: 291-296
1993
3		Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. VLSI Design 1993: 25-30
2	EE	Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm. IEEE Trans. VLSI Syst. 1(1): 22-30 (1993)
1992
1		Mario Kovac, N. Ranganathan, M. Varanasi: A Systolic Algorithm and Architecture for Galois Field Arithmetic. IPPS 1992: 283-288

Coauthor Index

1	N. Ranganathan (Nagarajan Ranganathan)	[1] [2] [3] [4] [5]
2	Davor Runje	[6]
3	M. Varanasi	[1] [2] [3]

Colors in the list of coauthors