George Economakos

2008
19	EE	George Economakos: Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis. BIBE 2008: 1-6
18	EE	Christoforos Economakos, George Economakos: Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis. ETFA 2008: 1002-1009
17	EE	Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos: A predecoding technique for ILP exploitation in Java processors. Journal of Systems Architecture - Embedded Systems Design 54(7): 707-728 (2008)
2007
16	EE	Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: A Reconfigurable Arithmetic Data-path Based On Regular Interconnection. AHS 2007: 342-349
15		George Economakos, Christoforos Economakos, Sotirios Xydis: Run-time reconfigurable solutions for adaptive control applications. ICINCO-SPSMC 2007: 208-213
14	EE	Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. ICSAMOS 2007: 137-144
2006
13	EE	George Economakos: High-level synthesis with reconfigurable datapath components. IPDPS 2006
12	EE	George Economakos: Behavioral synthesis with SystemC and PSL assertions for interface specification. ISCAS 2006
11	EE	George Economakos, K. Anagnostopoulos: Bit level architectural exploration technique for the design of low power multipliers. ISCAS 2006
2002
10	EE	George Economakos, Petros Oikonomakos, Ioannis Poulakis, George K. Papakonstantinou, Stamatis Georgoulis: Handling advanced scheduling heuristics under a hardware compiler generation environment. Knowl.-Based Syst. 15(1-2): 3-11 (2002)
2001
9	EE	George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou: Behavioral synthesis with systemC. DATE 2001: 21-25
8	EE	George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos: A Multi-Lingual Synthesis and Verification Environment. DSD 2001: 8-15
1999
7	EE	George Economakos, George K. Papakonstantinou: Refinement and Property Checking in High-Level Synthesis using Attribute Grammars. CHARME 1999: 330-333
6	EE	George Economakos, George K. Papakonstantinou: Language Based Design Verification with Semantic Analysis. EUROMICRO 1999: 1268-
1998
5	EE	George Economakos, George K. Papakonstantinou, Panayotis Tsanakas: AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. DATE 1998: 933-934
4	EE	George Economakos, George K. Papakonstantinou: Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment. EUROMICRO 1998: 10091-10098
3	EE	George Economakos, George K. Papakonstantinou, Panayotis Tsanakas: Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs. SAC 1998: 45-49
1997
2		George Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas: Hardware compilation using attribute grammars. CHARME 1997: 273-290
1		Nectarios Koziris, Theodore Andronikos, George Economakos, George K. Papakonstantinou, Panayotis Tsanakas: Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL. HPCN Europe 1997: 888-897

Coauthor Index

1	K. Anagnostopoulos	[11]
2	Theodore Andronikos	[1]
3	Christoforos Economakos	[15] [18]
4	Stamatis Georgoulis	[10]
5	Nectarios Koziris	[1]
6	Petros Oikonomakos	[9] [10]
7	Ioannis Panagopoulos	[9]
8	George K. Papakonstantinou	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
9	Kiamal Z. Pekmestzi	[2] [14] [16] [17]
10	Ioannis Poulakis	[9] [10]
11	Isidoros Sideris	[17]
12	Stergios Stergiou	[8]
13	Panayotis Tsanakas	[1] [2] [3] [5]
14	Sotirios Xydis	[14] [15] [16]
15	Vassilios Zoukos	[8]