| 2007 |
|---|
| 52 | EE | Matthias F. M. Stallmann,
Franc Brglez:
High-contrast algorithm behavior: observation, hypothesis, and experimental design.
Experimental Computer Science 2007: 12 |
| 51 | EE | Franc Brglez,
Jason A. Osborne:
Performance testing of combinatorial solvers with isomorph class instances.
Experimental Computer Science 2007: 13 |
| 2005 |
|---|
| 50 | EE | Xiao Yu Li,
Matthias F. M. Stallmann,
Franc Brglez:
Effective bounding techniques for solving unate and binate covering problems.
DAC 2005: 385-390 |
| 49 | EE | Franc Brglez,
Xiao Yu Li,
Matthias F. M. Stallmann:
On SAT instance classes and a method for reliable performance experiments with SAT solvers.
Ann. Math. Artif. Intell. 43(1): 1-34 (2005) |
| 2003 |
|---|
| 48 | EE | Xiao Yu Li,
Matthias F. M. Stallmann,
Franc Brglez:
A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation.
SAT 2003: 53-68 |
| 2001 |
|---|
| 47 | EE | Franc Brglez,
Hemang Lavana:
A Universal Client for Distributed Networked Design and Computing.
DAC 2001: 401-406 |
| 46 | | Matthias F. M. Stallmann,
Franc Brglez,
Debabrata Ghosh:
Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization.
ACM Journal of Experimental Algorithmics 6: 8 (2001) |
| 45 | EE | Justin E. Harlow III,
Franc Brglez:
Design of experiments and evaluation of BDD ordering heuristics.
STTT 3(2): 193-206 (2001) |
| 2000 |
|---|
| 44 | EE | Hemang Lavana,
Franc Brglez,
Robert B. Reese,
Gangadhar Konduri,
Anantha Chandrakasan:
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet.
ICCD 2000: 567-570 |
| 43 | EE | Franc Brglez:
The Scientific Method and Design and Test.
IEEE Design & Test of Computers 17(3): 142-144 (2000) |
| 1999 |
|---|
| 42 | EE | Matthias F. M. Stallmann,
Franc Brglez,
Debabrata Ghosh:
Heuristics and Experimental Design for Bigraph Crossing Number Minimization.
ALENEX 1999: 74-93 |
| 41 | EE | Franc Brglez,
Rolf Drechsler:
Design of experiments in CAD: context and new data sets for ISCAS'99.
ISCAS (6) 1999: 424-427 |
| 40 | EE | Debabrata Ghosh,
Franc Brglez:
Equivalence classes of circuit mutants for experimental design.
ISCAS (6) 1999: 432-435 |
| 39 | EE | Hemang Lavana,
Franc Brglez,
Robert B. Reese:
User-configurable experimental design flows on the web: the ISCAS'99 experiments.
ISCAS (6) 1999: 440-443 |
| 38 | EE | Matthias F. M. Stallmann,
Franc Brglez,
Debabrata Ghosh:
Evaluating iterative improvement heuristics for bigraph crossing minimization.
ISCAS (6) 1999: 444-447 |
| 37 | EE | Justin E. Harlow III,
Franc Brglez:
Mirror, mirror, on the wall...is the new release any different at all? [BDDs].
ISCAS (6) 1999: 452-455 |
| 1998 |
|---|
| 36 | EE | Debabrata Ghosh,
Nevin Kapur,
Franc Brglez,
Justin E. Harlow III:
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking.
DATE 1998: 656-663 |
| 35 | EE | Justin E. Harlow III,
Franc Brglez:
Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations.
FMCAD 1998: 64-81 |
| 34 | EE | Justin E. Harlow III,
Franc Brglez:
Design of experiments in BDD variable ordering: lessons learned.
ICCAD 1998: 646-652 |
| 33 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization.
ACM Trans. Design Autom. Electr. Syst. 3(2): 285-307 (1998) |
| 1997 |
|---|
| 32 | EE | Hemang Lavana,
Amit Khetawat,
Franc Brglez,
Krzysztof Kozminski:
Executable Workflows: A Paradigm for Collaborative Design on the Internet.
DAC 1997: 553-558 |
| 31 | EE | Hemang Lavana,
Amit Khetawat,
Franc Brglez:
Internet-based workflows: a paradigm for dynamically reconfigurable desktop environments.
GROUP 1997: 204-213 |
| 30 | EE | Nevin Kapur,
Debabrata Ghosh,
Franc Brglez:
Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions.
ISPD 1997: 136-143 |
| 1996 |
|---|
| 29 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Fast true delay estimation during high level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1088-1105 (1996) |
| 1995 |
|---|
| 28 | EE | Clay Gloster,
Franc Brglez:
Partial scan selection for user-specified fault coverage.
EURO-DAC 1995: 111-116 |
| 27 | EE | Roman Kuznar,
Franc Brglez:
PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists.
ICCAD 1995: 644-649 |
| 26 | EE | Andrej Zemva,
Franc Brglez:
Detectable perturbations: a paradigm for technology-specific multi-fault test generation.
VTS 1995: 350-357 |
| 1994 |
|---|
| 25 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Clock Period Optimization During Resource Sharing and Assignment.
DAC 1994: 195-200 |
| 24 | EE | Roman Kuznar,
Franc Brglez,
Baldomir Zajc:
Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect.
DAC 1994: 238-243 |
| 23 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications.
DAC 1994: 491-496 |
| 22 | | Andrej Zemva,
Franc Brglez,
Krzysztof Kozminski,
Baldomir Zajc:
A Functionality Fault Model: Feasibility and Applications.
EDAC-ETC-EUROASIC 1994: 152-158 |
| 21 | | Bernhard Rohfleisch,
Franc Brglez:
Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping.
EDAC-ETC-EUROASIC 1994: 87-93 |
| 20 | EE | Roman Kuznar,
Baldomir Zajc,
Franc Brglez:
A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions.
EURO-DAC 1994: 271-276 |
| 19 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Provably correct high-level timing analysis without path sensitization.
ICCAD 1994: 736-742 |
| 1993 |
|---|
| 18 | EE | Roman Kuznar,
Franc Brglez,
Krzysztof Kozminski:
Cost Minimization of Partitions into Multiple Devices.
DAC 1993: 315-320 |
| 17 | | Franc Brglez:
A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema?
IEEE Design & Test of Computers 10(3): 87-91 (1993) |
| 16 | EE | Subhrajit Bhattacharya,
Franc Brglez,
Sujit Dey:
Transformations and resynthesis for testability of RT-level control-data path specifications.
IEEE Trans. VLSI Syst. 1(3): 304-318 (1993) |
| 1992 |
|---|
| 15 | EE | Ulf Schlichtmann,
Franc Brglez,
Michael Hermann:
Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping.
DAC 1992: 374-379 |
| 14 | | Matthew Melton,
Franc Brglez:
Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults.
ITC 1992: 389-398 |
| 13 | EE | John D. Calhoun,
Franc Brglez:
A framework and method for hierarchical test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 45-67 (1992) |
| 1991 |
|---|
| 12 | | Sujit Dey,
Franc Brglez,
Gershon Kedem:
Partitioning Sequential Circuits for Logic Optimization.
ICCD 1991: 70-76 |
| 11 | | Sujit Dey,
Franc Brglez,
Gershon Kedem:
Identification and Resynthesis of Pipelines in Sequential Networks.
VLSI 1991: 439-449 |
| 1990 |
|---|
| 10 | EE | Sujit Dey,
Franc Brglez,
Gershon Kedem:
Corolla Based Circuit Partitioning and Resynthesis.
DAC 1990: 607-612 |
| 1989 |
|---|
| 9 | | Franc Brglez,
Gershon Kedem,
Clay Gloster:
Hardware-Based Weighted Random Pattern Generation for Boundary Scan.
ITC 1989: 264-274 |
| 8 | | John D. Calhoun,
Franc Brglez:
A Framework and Method for Hierarchical Test Generation.
ITC 1989: 480-490 |
| 1988 |
|---|
| 7 | | Clay Gloster,
Franc Brglez:
Boundary Scan with Cellular-Based Built-In Self-Test.
ITC 1988: 138-145 |
| 1987 |
|---|
| 6 | EE | Michael H. Schultz,
Franc Brglez:
Accelerated Transition Fault Simulation.
DAC 1987: 237-243 |
| 5 | EE | Robert Lisanke,
Franc Brglez,
Aart J. de Geus,
David Gregory:
Testability-Driven Random Test-Pattern Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 1082-1087 (1987) |
| 1985 |
|---|
| 4 | | Franc Brglez:
A Fast Fault Grader: Analysis and Applications.
ITC 1985: 785-794 |
| 3 | | Franc Brglez:
Fault Coverage Tools: Case Studies.
ITC 1985: 797-800 |
| 1984 |
|---|
| 2 | | Franc Brglez,
Philip Pownall,
Robert Hum:
Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing.
ITC 1984: 705-712 |
| 1981 |
|---|
| 1 | | Franc Brglez:
Digital Signal Processing Considerations in Filter-Codec Testing.
ITC 1981: 193-202 |
