| 2005 |
|---|
| 71 | EE | Eduard Cerny,
Ashvin Dsouza,
Kevin Harer,
Pei-Hsin Ho,
Hi-Keung Tony Ma:
Supporting sequential assumptions in hybrid verification.
ASP-DAC 2005: 1035-1038 |
| 2004 |
|---|
| 70 | EE | Ying Xu,
Xiaoyu Song,
Eduard Cerny,
Otmane Aït Mohamed:
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs).
Comput. J. 47(1): 71-84 (2004) |
| 69 | EE | Otmane Aït Mohamed,
Xiaoyu Song,
Eduard Cerny,
Sofiène Tahar,
Zijian Zhou:
MDG-Based State Enumeration By Retiming And Circuit Transformation.
Journal of Circuits, Systems, and Computers 13(5): 1111-1132 (2004) |
| 2003 |
|---|
| 68 | EE | Otmane Aït Mohamed,
Xiaoyu Song,
Eduard Cerny:
On the non-termination of M-based abstract state enumeration.
Theor. Comput. Sci. 300(1-3): 161-179 (2003) |
| 2002 |
|---|
| 67 | EE | Yi Feng,
Eduard Cerny:
Term ordering problem on MDG.
ACM Great Lakes Symposium on VLSI 2002: 160-165 |
| 66 | EE | Yi Feng,
Eduard Cerny:
Variable ordering on multiway decision graphs.
ISCAS (5) 2002: 337-340 |
| 2000 |
|---|
| 65 | EE | Jin Hou,
Eduard Cerny:
Model Reductions and a Case Study.
FMCAD 2000: 299-315 |
| 1999 |
|---|
| 64 | EE | Ying Xu,
Eduard Cerny,
Allan Silburt,
A. Coady,
Ying Liu,
Philip Pownall:
Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors.
CHARME 1999: 110-124 |
| 63 | EE | Eduard Cerny,
Fen Jin:
Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming.
ICCD 1999: 32-39 |
| 62 | EE | E. K. Ogoubi,
Eduard Cerny:
Synthesis of checker EFSMs from timing diagram specifications.
ISCAS (1) 1999: 13-18 |
| 61 | EE | Sophie Renault,
Eduard Cerny:
Improving Termination of MDG-Based Abstract State Enumeration via Term Schematization.
Electr. Notes Theor. Comput. Sci. 23(2): (1999) |
| 60 | EE | Abdessatar Abderrahman,
Eduard Cerny,
Bozena Kaminska:
Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 332-345 (1999) |
| 59 | EE | Sofiène Tahar,
Xiaoyu Song,
Eduard Cerny,
Zijian Zhou,
Michel Langevin,
Otmane Aït Mohamed:
Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 956-972 (1999) |
| 58 | EE | Samir Boubezari,
Eduard Cerny,
Bozena Kaminska,
Benoit Nadeau-Dostie:
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1327-1340 (1999) |
| 1998 |
|---|
| 57 | | Ying Xu,
Eduard Cerny,
Xiaoyu Song,
Francisco Corella,
Otmane Aït Mohamed:
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs.
CAV 1998: 219-231 |
| 56 | EE | Maroun Kassab,
Eduard Cerny,
Sidi Aourid,
Thomas H. Krodel:
Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis.
DATE 1998: 796-802 |
| 55 | EE | Eduard Cerny,
Fen Jin:
Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming.
EUROMICRO 1998: 10229-10236 |
| 54 | EE | Fen Jin,
Henrik Hulgaard,
Eduard Cerny:
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints.
FMCAD 1998: 167-184 |
| 53 | EE | Otmane Aït Mohamed,
Eduard Cerny,
Xiaoyu Song:
MDG-based Verification by Retiming and Combinational Transformations.
Great Lakes Symposium on VLSI 1998: 356-361 |
| 52 | EE | Karim Khordoc,
Eduard Cerny:
Semantics and verification of action diagrams with linear timing.
ACM Trans. Design Autom. Electr. Syst. 3(1): 21-50 (1998) |
| 1997 |
|---|
| 51 | | Otmane Aït Mohamed,
Xiaoyu Song,
Eduard Cerny:
On the non-termination of MDGs-based abstract state enumeration.
CHARME 1997: 218-235 |
| 50 | EE | Pierre Girodias,
Eduard Cerny:
Interface timing verification with delay correlation using constraint logic programming.
ED&TC 1997: 12-19 |
| 49 | | Eduard Cerny,
Francisco Corella,
Michel Langevin,
Xiaoyu Song,
Sofiène Tahar,
Zijian Zhou:
Verification with Abstract State Machines Using MDGs.
Formal Hardware Verification 1997: 79-113 |
| 48 | EE | Abdessatar Abderrahman,
Eduard Cerny,
Bozena Kaminska:
CLP-based Multifrequency Test Generation for Analog Circuits.
VTS 1997: 158-165 |
| 47 | | Francisco Corella,
Zijian Zhou,
Xiaoyu Song,
Michel Langevin,
Eduard Cerny:
Multiway Decision Graphs for Automated Hardware Verification.
Formal Methods in System Design 10(1): 7-46 (1997) |
| 46 | EE | Jocelyn Cloutier,
Eduard Cerny,
F. Guertin:
Model partitioning and the performance of distributed timewarp simulation of logic circuits.
Simul. Pr. Theory 5(1): 83-99 (1997) |
| 45 | EE | Pierre Girodias,
Eduard Cerny,
William J. Older:
Solving Linear, Min and Max Constraint Systems Using CLP Based on Relational Interval Arithmetic.
Theor. Comput. Sci. 173(1): 253-281 (1997) |
| 1996 |
|---|
| 44 | | K. D. Anon,
N. Boulerice,
Eduard Cerny,
Francisco Corella,
Michel Langevin,
Xiaoyu Song,
Sofiène Tahar,
Ying Xu,
Zijian Zhou:
MDG Tools for the Verification of RTL Designs.
CAV 1996: 433-436 |
| 43 | | Zijian Zhou,
Xiaoyu Song,
Sofiène Tahar,
Eduard Cerny,
Francisco Corella,
Michel Langevin:
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs.
FMCAD 1996: 233-247 |
| 42 | EE | Sofiène Tahar,
Zijian Zhou,
Xiaoyu Song,
Eduard Cerny,
Michel Langevin:
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs.
Great Lakes Symposium on VLSI 1996: 106-111 |
| 41 | EE | Michel Langevin,
Sofiène Tahar,
Zijian Zhou,
Xiaoyu Song,
Eduard Cerny:
Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration.
ICCD 1996: 20-26 |
| 40 | EE | Michel Langevin,
Eduard Cerny:
A recursive technique for computing lower-bound performance of schedules.
ACM Trans. Design Autom. Electr. Syst. 1(4): 443-455 (1996) |
| 39 | EE | Guy Bois,
Eduard Cerny:
Efficient generation of diagonal constraints for 2-D mask compaction.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1119-1126 (1996) |
| 38 | EE | Abdessatar Abderrahman,
Bozena Kaminska,
Eduard Cerny:
Optimization-based multifrequency test generation for analog circuits.
J. Electronic Testing 9(1-2): 59-73 (1996) |
| 1995 |
|---|
| 37 | | Francisco Corella,
Michel Langevin,
Eduard Cerny,
Zijian Zhou,
Xiaoyu Song:
State enumeration with abstract descriptions of state machines.
CHARME 1995: 146-160 |
| 36 | | Pierre Girodias,
Eduard Cerny,
William J. Older:
Solving Linear, Min and Max Constraint Systems Using CLP based on Relational Interval Arithmetic.
CP 1995: 186-203 |
| 35 | EE | Zijian Zhou,
Xiaoyu Song,
Francisco Corella,
Eduard Cerny,
Michel Langevin:
Partitioning transition relations efficiently and automatically.
Great Lakes Symposium on VLSI 1995: 106-111 |
| 1994 |
|---|
| 34 | | Michel Langevin,
Eduard Cerny,
Jörg Wilberg,
Heinrich Theodor Vierhaus:
Local microcode generation in system design.
Code Generation for Embedded Processors 1994: 171-187 |
| 33 | | Michel Langevin,
Eduard Cerny:
An Extended OBDD Representation for Extended FSMs.
EDAC-ETC-EUROASIC 1994: 208-213 |
| 32 | EE | Jindrich Zejda,
Eduard Cerny:
Gate-level timing verification using waveform narrowing.
EURO-DAC 1994: 374-379 |
| 31 | | Karim Khordoc,
Eduard Cerny:
Modeling Cell Processing Hardware with Action Diagrams.
ISCAS 1994: 245-248 |
| 30 | | Younès Karkouri,
El Mostapha Aboulhamid,
Eduard Cerny,
Alain Verreault:
Use of Fault Dropping for Multiple Fault Analysis.
IEEE Trans. Computers 43(1): 98-103 (1994) |
| 29 | | Jianli Sun,
Eduard Cerny,
Jan Gecsei:
Fault Tolerance in a Class of Sorting Networks.
IEEE Trans. Computers 43(7): 827-837 (1994) |
| 1993 |
|---|
| 28 | | Karim Khordoc,
Mario Dufresne,
Eduard Cerny,
P. A. Babkine,
Allan Silburt:
Integrating Behavior and Timing in Executable Specifications.
CHDL 1993: 399-416 |
| 27 | | Michel Langevin,
Eduard Cerny:
A Recursive Technique for Computing Lower-Bound Performance of Schedules.
ICCD 1993: 16-20 |
| 26 | EE | El Mostapha Aboulhamid,
Younès Karkouri,
Eduard Cerny:
On the generation of test patterns for multiple faults.
J. Electronic Testing 4(3): 237-253 (1993) |
| 1992 |
|---|
| 25 | | Eduard Cerny:
Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines.
ICCD 1992: 526-530 |
| 24 | EE | Mohamed Meknassi,
El Mostapha Aboulhamid,
Eduard Cerny:
Algorithm for the graph-partitioning problem using a problem transformation method.
Computer-Aided Design 24(7): 397-398 (1992) |
| 23 | EE | Eduard Cerny,
John P. Hayes,
Nicholas C. Rumin:
Accuracy of magnitude-class calculations in switch-level modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 443-452 (1992) |
| 1991 |
|---|
| 22 | | Michel Langevin,
Eduard Cerny:
Comparing Generic State Machines.
CAV 1991: 466-476 |
| 21 | | Karim Khordoc,
Mario Dufresne,
Eduard Cerny:
A Stimulus/Response System Based on Hierarchical Timing Diagrams.
ICCAD 1991: 358-361 |
| 20 | | Eduard Cerny:
A Compositional Transformation for Formal Verification.
ICCD 1991: 240-244 |
| 19 | EE | Jean Paul Caisso,
Eduard Cerny,
Nicholas C. Rumin:
A recursive technique for computing delays in series-parallel MOS transistor circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 589-595 (1991) |
| 1990 |
|---|
| 18 | | Eduard Cerny,
C. Mauras:
Tautology Checking Using Cross-Controllability and Cross-Observability Relations.
ICCAD 1990: 34-37 |
| 17 | EE | Jianli Sun,
Jan Gecsei,
Eduard Cerny:
Fault-tolerance in balanced sorting networks.
J. Electronic Testing 1(1): 31-41 (1990) |
| 1988 |
|---|
| 16 | | Eduard Cerny,
Jan Gecsei:
Functional Description of Connector-Switch-Attenuator Networks.
IEEE Trans. Computers 37(1): 111-114 (1988) |
| 15 | | Christian Berthet,
Eduard Cerny:
An Algebraic Model for Asynchronous Circuits Verification.
IEEE Trans. Computers 37(7): 835-847 (1988) |
| 1987 |
|---|
| 14 | EE | L.-P. Demers,
P. Jacques,
S. Fauvel,
Eduard Cerny:
CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools.
DAC 1987: 750-756 |
| 13 | | Jan Gecsei,
Eduard Cerny:
Self-Adjusting Networks for VLSI Simulation.
IEEE Trans. Computers 36(9): 1114-1120 (1987) |
| 12 | | Behçet Sarikaya,
Gregor von Bochmann,
Eduard Cerny:
A Test Design Methodology for Protocol Testing.
IEEE Trans. Software Eng. 13(5): 518-531 (1987) |
| 1985 |
|---|
| 11 | EE | C. Roy,
L.-P. Demers,
Eduard Cerny,
Jan Gecsei:
An object-oriented swicth-level simulator.
DAC 1985: 623-629 |
| 10 | EE | Eduard Cerny,
Jan Gecsei:
Simulation of MOS Circuits by Decision Diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(4): 685-693 (1985) |
| 1984 |
|---|
| 9 | | Gregor von Bochmann,
Eduard Cerny,
G. Gerber,
Rachida Dssouli,
Michel Maksud,
B. H. Phan,
Behçet Sarikaya,
Jean-Marc Serre:
Use of Formal Specifications for Protocol Design, Implementation and Testing.
PSTV 1984: 137-144 |
| 8 | EE | Eduard Cerny:
Some issues in protocol implementation testing.
Computer Communication Review 14(2): 259-260 (1984) |
| 7 | | El Mostapha Aboulhamid,
Eduard Cerny:
Built-In Testing of One-Dimensional Unilateral Iterative Arrays.
IEEE Trans. Computers 33(6): 560-564 (1984) |
| 1983 |
|---|
| 6 | | El Mostapha Aboulhamid,
Eduard Cerny:
A Class of Test Generators for Built-In Testing.
IEEE Trans. Computers 32(10): 957-959 (1983) |
| 1982 |
|---|
| 5 | | Gregor von Bochmann,
Eduard Cerny,
Michel Gagne,
Claude Jard,
Alain Léveillé,
Clement Lacaille,
Michel Maksud,
K. S. Raghunathan,
Behçet Sarikaya:
Some Experience with the Use of Formal Specifications.
PSTV 1982: 171-185 |
| 1979 |
|---|
| 4 | | Eduard Cerny,
Daniel Mange,
Eduardo Sanchez:
Synthesis of Minimal Binary Decision Trees.
IEEE Trans. Computers 28(7): 472-482 (1979) |
| 1978 |
|---|
| 3 | | Eduard Cerny:
Controllability and Fault Observability in Modular Combinational Circuits.
IEEE Trans. Computers 27(10): 896-903 (1978) |
| 1977 |
|---|
| 2 | | Eduard Cerny,
Miguel A. Marin:
An Approach to Unified Methodology of Combinational Switching Circuits.
IEEE Trans. Computers 26(8): 745-756 (1977) |
| 1976 |
|---|
| 1 | | Eduard Cerny:
Comments on ``Equational Logic''.
IEEE Trans. Computers 25(1): 102-103 (1976) |
