ITC 1991:
Nashville,
TN,
USA
Proceedings IEEE International Test Conference 1991, Test: Faster, Better, Sooner, Nashville, TN, USA, October 26-30, 1991.
IEEE Computer Society 1991, ISBN 0-8186-9156-5 BibTeX
@proceedings{DBLP:conf/itc/1991,
title = {Proceedings IEEE International Test Conference 1991, Test: Faster,
Better, Sooner, Nashville, TN, USA, October 26-30, 1991},
booktitle = {ITC},
publisher = {IEEE Computer Society},
year = {1991},
isbn = {0-8186-9156-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Plenary
Keynote Address
- Phil Robinson:
Concurrent Engineering: Creating Designs That Are Faster, Better and Available Sooner.
19 BibTeX
Session 2:
Practical BIST Implementation Case Studies
Session 3:
Sequential ATPG
Session 4:
Boundary Scan:
Test and Diagnostics of the Infrastructure
Session 5:
Case Studies in VLSI Chip Testing
- Jose A. Lyon, Mike Gladden, Eytan Hartung, Eric Hoang, K. Raghunathan:
Testability Features of the 68HC16Z1.
122-130 BibTeX
- P. Thorel, J. L. Rainard, A. Botta, A. Chemarin, J. Majos:
Implementing Boundary-Scan and Pseudo-Random BIST in an Asynchronous Transfer Mode Switch.
131-139 BibTeX
- Johan Karlsson, Ulf Gunneflo, Peter Lidén, Jan Torin:
Two Fault Injection Techniques for Test of Fault Handling Mechanisms.
140-149 BibTeX
- Tony Cheng, Eric Hoang, David Rivera, Alan Haedge, Jamie Fontenot, Glenn Carson:
Test Grading the 68332.
150-156 BibTeX
Session 6:
DFT:
New Algorithms for Automation Tools
Session 7:
Test Generation and Compaction
Session 8:
Using Test Results for Process Improvement
Session 9:
Contactless Probing
Session 10:
DFT:
Advanced Design and Analysis Techniques
Session 11:
Physical Defects and Analysis 1
Session 12:
Computer Assisted Diagnosis and Repair
Session 13:
Specialized Quality Topics
Session 14:
Scan Design:
Innovations and Enhancements
Session 15:
Delay Faults and Bridging Faults
Session 16:
ATE Architecture and Methods
Session 17:
Statistics and Test - Working Together
Session 18:
BIST Issues in Logic Synthesis
Session 19:
Physical Defects and Analysis 2
Session 20:
Diagnosis and Repair of Complex Custom Circuits
Session 21:
Test Techniques as Applied to Memory Devices
Session 22:
Mixed Signal Test Generation Based on Fault Modeling
Session 23:
CAE for IDDq Testing
Session 24:
Board Test:
The Future Is Arriving
Session 25:
Algorithms and Fault Modeling for Testing Memory Devices
Session 26:
Test Pattern Generation Issues in BIST
Session 27:
Hierarchical Test Generation
Session 28:
System Testing
Session 29:
ATE Implementation and Application
Session 30:
Response Compaction Issues in BIST
Session 31:
Testing a Higher Level of Integration
Session 32:
Boundary Scan - Dealing with Chip Implementation
Session 33:
Synthesis for Test
Session 34:
Concurrent BIST Design and Verification
Session 35:
Fast Fault Simulation and Multiple Faults
Session 36:
AC Test Calibration and Accuracy
Session 37:
Software Techniques Improve Use of Test Resources 1
Session 38:
DFT Applications and Experience
Session 39:
Innovations in Mixed Signal Test Equipment
Session 40:
A Potpourri of Test
Session 41:
Software Techniques Improve Use of Test Resources 2
Panel 1:
Open Meeting:
Languages to Support Boundary-Scan Test
Panel 2:
Software Testing - State of the Practice
Panel 4:
Acceptance Barriers Confronting DFT and BIST
Panel 5:
Is Burn-In Burned Out?
Panel 6:
Quality in Test Education?
International Test Conference 1990 Best Paper
Copyright © Sat May 16 23:26:41 2009
by Michael Ley (ley@uni-trier.de)
