ICCD 1995:
Austin,
Texas,
USA
1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings.
IEEE Computer Society 1995, ISBN 0-8186-7165-3 BibTeX
@proceedings{DBLP:conf/iccd/1995,
title = {1995 International Conference on Computer Design (ICCD '95),
VLSI in Computers and Processors, October 2-4, 1995, Austin,
TX, USA, Proceedings},
publisher = {IEEE Computer Society},
year = {1995},
isbn = {0-8186-7165-3},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Architecture/Algorithms Plenary
Signal propagation in high-speed MCM circuits
Asynchronous Systems
Embedded System Analysis
Issues in Superscalar Processors
- Steven Wallace, Nirav Dagli, Nader Bagherzadeh:
Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor.
96-101
Electronic Edition (IEEE Computer Society DL) BibTeX
- Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa:
A superscalar RISC processor with pseudo vector processing feature.
102-109
Electronic Edition (IEEE Computer Society DL) BibTeX
- John-David Wellman, Edward S. Davidson:
The resource conflict methodology for early-stage design space exploration of superscalar RISC processors.
110-
Electronic Edition (IEEE Computer Society DL) BibTeX
SPARC Design Methodologies
Simulation
Design for Testability
PowerPC(tm)
- Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore:
The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor.
196-203
Electronic Edition (IEEE Computer Society DL) BibTeX
- Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington:
A high performance bus and cache controller for PowerPC multiprocessing systems.
204-211
Electronic Edition (IEEE Computer Society DL) BibTeX
- Charles P. Roth, Frank E. Levine, Edward H. Welbon:
Performance monitoring on the PowerPC 604 microprocessor.
212-
Electronic Edition (IEEE Computer Society DL) BibTeX
Floor Planning & Placement
Combinational and Sequential Logic Optimization
Massively Parallel Processing Interconnects
Test Pattern Generation
Caching Strategies
Embedded System Architecture & Case Studies
ATM and High-Speed Networking Alternatives
Routing & Extraction
Asynchronous Datapaths
FPGA - Synthesis
Design & Test Plenary
Topics in High-Level Synthesis
Low Power and High-Performance Circuits
Arithmetic Modules
Architectures for Signal Processors
Memory System Performance
Emerging Technologies for Processor Verification
Memory Architectures for Signal Processing
- Martin C. Herbordt, Charles C. Weems:
An empirical study of datapath, memory hierarchy, and network in SIMD array architectures.
546-551
Electronic Edition (IEEE Computer Society DL) BibTeX
- Eddy de Greef, Francky Catthoor, Hugo De Man:
Memory organization for video algorithms on programmable signal processors.
552-557
Electronic Edition (IEEE Computer Society DL) BibTeX
- Shigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito:
SSM-MP: more scalability in shared-memory multi-processor.
558-
Electronic Edition (IEEE Computer Society DL) BibTeX
Novel Design Concepts
FSM Verification
Fault Simulation
Application-Specific Processors
Performance Driven Synthesis
Copyright © Sat May 16 23:16:38 2009
by Michael Ley (ley@uni-trier.de)