11. VLSI Design 1998:
Chennai,
India
11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India.
IEEE Computer Society 1998 BibTeX
Plenary Session
Low Power Design Methodologies
- Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters.
12-17
Electronic Edition (link) BibTeX
- Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications.
18-23 BibTeX
- Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
A Power Management Methodology for High-Level Synthesis.
24-19 BibTeX
- Suhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar:
Freedom: Statistical Behavioral Estimation of System Energy and Power.
30-36
Electronic Edition (link) BibTeX
- Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Extensions to Programmable DSP architectures for Reduced Power Dissipation.
37-
Electronic Edition (link) BibTeX
Physical Design
System Design and Synthesis
- Neil Weste, David J. Skellern, Terry Percival:
Invited Paper: Broadband U-NII Wireless Data.
72-77 BibTeX
- Bengt Svantesson, Shashi Kumar, Ahmed Hemani:
A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL.
78-84 BibTeX
- Anupam Basu, Raj S. Mitra, Peter Marwedel:
Interface Synthesis for Embedded Applications in a Co Design Environment.
85-90
Electronic Edition (link) BibTeX
- Pradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta:
Hardware/Software Co-design of a High-end Mixed Signal Microcontroller.
91-96
Electronic Edition (link) BibTeX
- Sandeep K. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee:
Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign.
97- BibTeX
Digital Signal Processing
Analog Techniques
Test Synthesis
- Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel:
Partial Scan Selection Based on Dynamic Reachability and Observability Information.
174-180
Electronic Edition (link) BibTeX
- Arun Balakrishnan, Srimat T. Chakradhar:
Peripheral Partitioning and Tree Decomposition for Partial Scan.
181-186
Electronic Edition (link) BibTeX
- C. P. Ravikumar, Sumit Gupta, Akshay Jajoo:
Synthesis of Testable RTL Designs.
187-192 BibTeX
- Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.
193-198
Electronic Edition (link) BibTeX
- Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee:
Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits.
199-204 BibTeX
- Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya:
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults.
205-
Electronic Edition (link) BibTeX
Logic Level CAD
- Sumit Roy, Prithviraj Banerjee, Majid Sarrafzadeh:
Partitioning sequential circuits for low power.
212-217
Electronic Edition (link) BibTeX
- Pramit Chavda, James Jacob, Vishwani D. Agrawal:
Optimizing Logic Design Using Boolean Transforms.
218-221
Electronic Edition (link) BibTeX
- Aarti Gupta, Pranav Ashar:
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.
222-225
Electronic Edition (link) BibTeX
- Abhijit Das, Samrat Sen, Mohan Rangan, Rupesh Nayak, G. N. Nandakumar:
False Path Detection at Transistor Level.
226-229 BibTeX
- Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan:
Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach.
230-233 BibTeX
- Raghu Burra, Dinesh Bhatia:
Timing Driven Multi-FPGA Board Partitioning.
234-
Electronic Edition (link) BibTeX
Analog / Physical Design
- Adriano M. Pereira, Tales Cleber Pimenta, Robson L. Moreno, Edgar Charry R., Alberto M. Jorge:
Design of a Measurement and Interface Integrated Circuit for Characterization of Switched Current Memory Cells.
240-243
Electronic Edition (link) BibTeX
- Saeid Nooshabadi, G. S. Visweswaran, D. Nagchoudhuri:
Current Mode Ternary D/A Converter.
244-248 BibTeX
- Prakash Gopalakrishnan, Vinita Vasudevan:
A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits.
249-252
Electronic Edition (link) BibTeX
- Nagu R. Dhanwada, Ranga Vemuri:
Constraint Allocation in Analog System Synthesis.
253-258
Electronic Edition (link) BibTeX
- Gregory E. Beers, Lizy Kurian John:
Novel Memory Bus Driver/Receiver Architecture for Higher Throughput.
259-264
Electronic Edition (link) BibTeX
- Cyrus Bamji, Ravi Varadarajan:
Incremental Autojogging using Range Spaces.
265-
Electronic Edition (link) BibTeX
Topics in Testing
Banquet Session
Plenary Session
VLSI Architecture and Arithmetic
- S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, A. Karmakar, Chandra Shekhar, Sudhir Kumar, Amit K. Agarwal:
Evolution of Architectural Concepts and Design Methods of Microprocessors.
312-317
Electronic Edition (link) BibTeX
- Giuseppe Ascia, Vincenzo Catania:
A Framework for a Parallel Architecture Dedicated to Soft Computing.
318-321
Electronic Edition (link) BibTeX
- Bernard Laurent, G. Bosco, Gabriele Saucier:
Fast Arithmetic on Xilinx 5200 FPGA.
322-325
Electronic Edition (link) BibTeX
- S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, M. S. Diamondstein:
VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay.
326-329
Electronic Edition (link) BibTeX
- R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili:
A Low Power Floating Point Accumulator.
330-
Electronic Edition (link) BibTeX
Simulation and Synthesis
Delay Test and Defect Analysis
Reconfigurable Processors and ASIC Design
- Henry Selvaraj, Miroslawa Nowicka, Tadeusz Luba:
Decomposition Strategies and their Performance in Fpga-Based Technology Mapping.
388-393
Electronic Edition (link) BibTeX
- M. Bhaskar Sherigar, A. S. Mahadevan, K. Senthil Kumar, Sumam David:
A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA.
394-399 BibTeX
- Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar:
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.
400-405 BibTeX
- P. S. Nagendra Rao, C. S. Jayathirtha, C. S. Raghavendra Prasad:
New Net Models for Spectral Netlist Partitioning.
406
Electronic Edition (link) BibTeX
- Atul Wokhlu, R. Venkat Krishna, Sandeep Agarwal:
A Low Voltage Mixed Signal ASIC for Digital Clinical Thermometer.
412-
Electronic Edition (link) BibTeX
Architecture and System Design Tools
Simulation and Test
Circuit Analysis and Design
Logic and Circuit Synthesis
Design Verification
Panel Session
- Hugo De Man:
Invited Address: Future Systems-on-a-Chip: Impact on Engineering Education.
572-577 BibTeX
- Rajeev Jain:
Panel: Challenges for Future Systems on a Chip.
578- BibTeX
Copyright © Sat May 16 23:46:42 2009
by Michael Ley (ley@uni-trier.de)
