| |
| 1999 | ||
|---|---|---|
| 2 | Sitaran Yadavalli, Sudhakar M. Reddy: SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level. ITC 1999: 606-615 | |
| 1995 | ||
| 1 | EE | Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy: MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. VLSI Design 1995: 110-115 |
| 1 | Irith Pomeranz | [1] |
| 2 | Sudhakar M. Reddy | [1] [2] |