30. DAC 1993:
Dallas,
Texas,
USA
Proceedings of the 30th Design Automation Conference. Dallas,
Texas,
USA,
June 14-18,
1993. ACM Press,
1993,
ISBN 0-89791-577-1
Asynchronous Circuit Design
Sequential Circuit Analysis and Optimization
Fast Algorithm for Layout Analysis
Increasing Design Quality and Engineering Productivity through Design Reuse
New Ideas in Technology Mapping
- Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, J. Yang:
Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping.
54-60
Electronic Edition (ACM DL) BibTeX
- Polly Siegel, Giovanni De Micheli, David L. Dill:
Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs.
61-67
Electronic Edition (ACM DL) BibTeX
- Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain:
Technology Decomposition and Mapping Targeting Low Power Dissipation.
68-73
Electronic Edition (ACM DL) BibTeX
- Vivek Tiwari, Pranav Ashar, Sharad Malik:
Technology Mapping for Lower Power.
74-79
Electronic Edition (ACM DL) BibTeX
Test Generation
- Irith Pomeranz, Sudhakar M. Reddy:
INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning.
80-85
Electronic Edition (ACM DL) BibTeX
- Kwang-Ting Cheng, A. S. Krishnakumar:
Automatic Functional Test Generation Using the Extended Finite State Machine Model.
86-91
Electronic Edition (ACM DL) BibTeX
- Jean François Santucci, Anne-lise Courbis, Norbert Giambiasi:
Speed up of Behavioral A.T.P.G. using a Heuristic Criterion.
92-96
Electronic Edition (ACM DL) BibTeX
- Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin:
A State Traversal Algorithm Using a State Covariance Matrix.
97-101
Electronic Edition (ACM DL) BibTeX
- Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits.
102-106
Electronic Edition (ACM DL) BibTeX
- Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo:
Sequential Circuit Test Generation on a Distributed System.
107-111
Electronic Edition (ACM DL) BibTeX
Timing Estimation and Verification
Panel
Optimization of Analog Circuits
Panel
Optimal Tree Construction
- Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage:
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization.
165-170
Electronic Edition (ACM DL) BibTeX
- Andrew Lim, Siu-Wing Cheng, Ching-Ting Wu:
Performance Oriented Rectilinear Steiner Trees.
171-176
Electronic Edition (ACM DL) BibTeX
- Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang:
Performance-Driven Steiner Tree Algorithm for Global Routing.
177-181
Electronic Edition (ACM DL) BibTeX
- Kenneth D. Boese, Andrew B. Kahng, Gabriel Robins:
High-Performance Routing Trees With Identified Critical Sinks.
182-187
Electronic Edition (ACM DL) BibTeX
High Level Design Implementation
Technology Mapping for FPGAS and Layout
Design for Test
Extending the Applicability of BDDs
Information Modeling
Panel
System Implementation Issues
Panel
FPGA Layout and Partitioning
EDAC User Session
DSP Synthesis
Simulation and Analysis of Digital Circuits
Large-Scale Compaction
- Cyrus Bamji, Ravi Varadarajan:
MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction.
389-394
Electronic Edition (ACM DL) BibTeX
- So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo:
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP.
395-400
Electronic Edition (ACM DL) BibTeX
- Peichen Pan, Sai-keung Dong, C. L. Liu:
Optimal Graph Constraint Reduction for Symbolic Layout Compaction.
401-406
Electronic Edition (ACM DL) BibTeX
- Joseph Dao, Nobu Matsumoto, Tsuneo Hamai, Chusei Ogawa, Shojiro Mori:
A Compaction Method for Full Chip VLSI Layouts.
407-412
Electronic Edition (ACM DL) BibTeX
Issues in System Design
Testing of Delay and Bridging Faults
Formal Verification
Panel
Retiming and Timing Analysis in Sequential Synthesis
Fault Simulation and Diagnosis
Placement and Floorplanning
Practical Design and Validation Techniques
Retiming and Scheduling
- Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha:
Rotation Scheduling: A Loop Pipelining Algorithm.
566-572
Electronic Edition (ACM DL) BibTeX
- Zia Iqbal, Miodrag Potkonjak, Sujit Dey, Alice C. Parker:
Critical Path Minimization Using Retiming and Algebraic Speed-Up.
573-577
Electronic Edition (ACM DL) BibTeX
- S. H. Huang, Y. L. Jeang, C. T. Hwang, Y. C. Hsu, J. F. Wang:
A Tree-Based Scheduling Algorithm for Control-Dominated Circuits.
578-582
Electronic Edition (ACM DL) BibTeX
- Richard J. Cloutier, Donald E. Thomas:
Synthesis of Pipelined Instruction Set Processors.
583-588
Electronic Edition (ACM DL) BibTeX
Panel
Performance-Driven Routing
Panel
Advances in Logic Synthesis
- Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Espresso-Signature: A New Exact Minimizer for Logic Functions.
618-624
Electronic Edition (ACM DL) BibTeX
- Olivier Coudert, Jean Christophe Madre, Henri Fraisse:
A New Viewpoint on Two-Level Logic Minimization.
625-630
Electronic Edition (ACM DL) BibTeX
- Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli:
Optimization of Combinational Logic Circuits Based on Compatible Gates.
631-636
Electronic Edition (ACM DL) BibTeX
- Hans Eveking, Stefan Höreth:
Optimization and Resynthesis of Complex Data-Paths.
637-641
Electronic Edition (ACM DL) BibTeX
- Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula:
BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis.
642-647
Electronic Edition (ACM DL) BibTeX
Infrastructure from Process to Debugging
High Speed Interconnects Analysis
Russian CAE
Electrical Modeling and Simulation
Panel
Circuit Partitioning
Panel
Copyright © Sat May 16 23:04:36 2009
by Michael Ley (ley@uni-trier.de)