16. VLSI Design 2003:
New Delhi,
India
16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India.
IEEE Computer Society 2003, ISBN 0-7695-1868-0 BibTeX
@proceedings{DBLP:conf/vlsid/2003,
title = {16th International Conference on VLSI Design (VLSI Design 2003),
4-8 January 2003, New Delhi, India},
booktitle = {VLSI Design},
publisher = {IEEE Computer Society},
year = {2003},
isbn = {0-7695-1868-0},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Speeches
Tutorials
- Sandeep K. Shukla, Jean-Pierre Talpin, Stephen A. Edwards, Rajesh K. Gupta:
High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap.
9-14
Electronic Edition (link) BibTeX
- Rajiv V. Joshi, Kaushik Roy:
Design of Deep Sub-Micron CMOS Circuits.
15-16
Electronic Edition (link) BibTeX
- Rubin A. Parekhji:
Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.
17
Electronic Edition (link) BibTeX
- Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran:
Specification and Design of Multi-Million Gate SOCs.
18-19
Electronic Edition (link) BibTeX
- Natarajan Mahadeva Iyer, M. K. Radhakrishnan:
ESD Reliability Challenges for RF/Mixed Signal Design & Processing.
20-21
Electronic Edition (link) BibTeX
- Krithi Ramamritham, Kavi Arya:
System Support for Embedded Applications.
22-
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Analog and RF Devices
Physical Design
FPGA
MOS Technology
- Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao:
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.
99-104
Electronic Edition (link) BibTeX
- R. Srinivasan, Navakanta Bhat:
Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's.
105-109
Electronic Edition (link) BibTeX
- Najeebuddin Hakim, V. Ramgopal Rao, J. Vasi:
Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications.
110-115
Electronic Edition (link) BibTeX
- Manisha Pattanaik, Swapna Banerjee:
A New Approach to Analyze a Sub-micron CMOS Inverter.
116-121
Electronic Edition (link) BibTeX
- Vinod Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau:
Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node.
122-127
Electronic Edition (link) BibTeX
- D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao:
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.
128-
Electronic Edition (link) BibTeX
ATPG and DFT
- Arun Krishnamachary, Jacob A. Abraham:
Effects of Multi-cycle Sensitization on Delay Tests.
137-142
Electronic Edition (link) BibTeX
- Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja:
Exclusive Test and its Applications to Fault Diagnosis.
143-148
Electronic Edition (link) BibTeX
- Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell:
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification.
149-154
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- Samir Roy, U. Maulik, Biplab K. Sikdar:
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines.
155-160
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- Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Design Of A Universal BIST (UBIST) Structure.
161-166
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- Petros Drineas, Yiorgos Makris:
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs.
167-
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VLSI Processors
- Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar:
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.
177-182
Electronic Edition (link) BibTeX
- Vadali Srinivasa Murty, P. C. Reghu Raj, S. Raman:
Design of a high speed string matching co-processor for NLP.
183-188
Electronic Edition (link) BibTeX
- Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli:
A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems.
189-194
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- Kyriakos Vlachos, Nikos A. Nikolaou, Theofanis Orphanoudakis, Stylianos Perissakis, Dionisios N. Pnevmatikatos, George Kornaros, J. A. Sanchez, George E. Konstantoulakis:
Processing and Scheduling Components in an Innovative Network Processor Architecture.
195-201
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- Srikar Movva, S. Srinivasan:
A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI.
202-207
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- Bipul Das, Swapna Banerjee:
A Memory Efficient 3-D DWT Architecture.
208-
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Memory Technology
Verification and Synthesis
Security
- Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
Embedding Security in Wireless Embedded Systems.
269-270
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- Subhayan Sen, Sk. Iqbal Hossain, Kabirul Islam, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri:
Cryptosystem Designed for Embedded System Security.
271-276
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- Chandrama Shaw, Debashis Chatterji, Pradipta Maji, Subhayan Sen, B. N. Roy, Parimal Pal Chaudhuri:
A Pipeline Architecture for Encompression (Encryption + Compression) Technology.
277-282
Electronic Edition (link) BibTeX
- Annajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan:
VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images.
283-
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Low-Power Technologies
Test Optimization
- Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa:
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs.
329-334
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.
335-340
Electronic Edition (link) BibTeX
- Santanu Chattopadhyay, K. Sudarsana Reddy:
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips.
341-346
Electronic Edition (link) BibTeX
- C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra:
Mutual Testing based on Wavelet Transforms.
347-352
Electronic Edition (link) BibTeX
- Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal:
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.
353-360
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- Sagar S. Sabade, D. M. H. Walker:
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification.
361-
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System-on-a-Chip
- Jiong Luo, Niraj K. Jha:
Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems.
369-375
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- Thomas Wild, Jürgen Foag, Nuria Pazos, Winthir Brunnbauer:
Mapping and Scheduling for Architecture Exploration of Networking SoCs.
376-381
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- Praveen Bhojwani, Rabi N. Mahapatra:
Interfacing Cores with On-chip Packet-Switched Networks.
382-387
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- Robert H. Bell Jr., Lizy Kurian John:
Interface Design Techniques for Single-Chip Systems.
388-394
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- Bedabrata Pain, Bruce Hancock, Thomas Cunningham, Guang Yang, Suresh Seshadri, Julie Heynssens, Chris Wrigley:
CMOS Digital Imager Design from a System-on-a-chip Perspective.
395-400
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- Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar:
Extending Platform-Based Design to Network on Chip Systems.
401-
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Coupling Effects
Power Estimation and Control
High-Level Synthesis
- Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau:
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations.
461-466
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- Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey:
High-level Synthesis of Multi-process Behavioral Descriptions.
467-473
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- G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja:
Graph Transformations for Improved Tree Height Reduction.
474-479
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- Keith S. Vallerio, Niraj K. Jha:
Task Graph Extraction for Embedded System Synthesis.
480-
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Device Design
- M. Jagadesh Kumar, D. Venkateshrao:
A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design.
489-492
Electronic Edition (link) BibTeX
- Alejandro F. González, Pinaki Mazumder:
Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes.
493-492
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- Abhisek Dixit, V. Ramgopal Rao:
A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime.
499-503
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- Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri:
A Low Voltage Switched-Capacitor Current Reference Circuit with low dependence on Process, Voltage and Temperature.
504-506
Electronic Edition (link) BibTeX
- Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi, P. K. Ghosh:
Synthesis Of Programmable Current Mode Linear Analog Circuit.
507-512
Electronic Edition (link) BibTeX
- Geun Rae Cho, Tom Chen:
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment.
513-
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Low-Power Design/Test
- Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin:
A Low Power-Delay Product Page-Based Address Bus Coding Method.
521-526
Electronic Edition (link) BibTeX
- Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.
527-532
Electronic Edition (link) BibTeX
- Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz:
GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment.
533-538
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- Saraju P. Mohanty, N. Ranganathan:
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis.
539-545
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- Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang:
Low-Energy BIST Design for Scan-based Logic Circuits.
546-551
Electronic Edition (link) BibTeX
- Santanu Chattopadhyay, Naveen Choudhary:
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing.
552-
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Reconfigurable System Software
- Kiran Puttegowda, William Worek, Nicholas Pappas, Anusha Dandapani, Peter Athanas, Allan Dickerman:
A Run-Time Reconfigurable System for Gene-Sequence Searching.
561-566
Electronic Edition (link) BibTeX
- Wu Jigang, Thambipillai Srikanthan:
A Run-time Reconfiguration Algorithm for VLSI Arrays.
567-572
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- T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravi Kumar:
Optimal Code and Data Layout in Embedded Systems.
573-578
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- Pao-Ann Hsiung, Feng-Shi Su:
Synthesis of Real-Time Embedded Software by Timed Quasi-Static Scheduling.
579-584
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- Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar:
SoC Synthesis with Automatic Hardware Software Interface Generation.
585-
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:46:43 2009
by Michael Ley (ley@uni-trier.de)
