Volume 48,
Number 1,
January 1999
Computer Arithmetic
Software Testing
Fault Tolerance
Real-Time Systems
Brief Contributions
Volume 48,
Number 2,
February 1999
Special Issue on Cache Memory and Related Problems
Uniprocessing
- Jih-Kwon Peir, Windsor W. Hsu, Alan Jay Smith:
Functional Implementation Techniques for CPU Cache Memories.
100-110
Electronic Edition (IEEE Computer Society DL) BibTeX
- Eric Rotenberg, Steve Bennett, James E. Smith:
A Trace Cache Microarchitecture and Evaluation.
111-120
Electronic Edition (IEEE Computer Society DL) BibTeX
- Doug Joseph, Dirk Grunwald:
Prefetching Using Markov Predictors.
121-133
Electronic Edition (IEEE Computer Society DL) BibTeX
- Chi-Keung Luk, Todd C. Mowry:
Automatic Compiler-Inserted Prefetching for Pointer-Based Applications.
134-141
Electronic Edition (IEEE Computer Society DL) BibTeX
- Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau:
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.
142-149
Electronic Edition (IEEE Computer Society DL) BibTeX
- Olivier Temam:
An Algorithm for Optimally Exploiting Spatial and Temporal Locality in Upper Memory Levels.
150-158
Electronic Edition (IEEE Computer Society DL) BibTeX
- Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary:
Improving Cache Locality by a Combination of Loop and Data Transformation.
159-167
Electronic Edition (IEEE Computer Society DL) BibTeX
- John Kalamatianos, Alireza Khalafi, David R. Kaeli, Waleed Meleis:
Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance.
168-175
Electronic Edition (IEEE Computer Society DL) BibTeX
- Hantak Kwak, Ben Lee, Ali R. Hurson, Suk-Han Yoon, Woo-Jong Hahn:
Effects of Multithreading on Cache Performance.
176-184
Electronic Edition (IEEE Computer Society DL) BibTeX
- Nigel P. Topham, Antonio González:
Randomized Cache Placement for Eliminating Conflicts.
185-192
Electronic Edition (IEEE Computer Society DL) BibTeX
- Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt:
Evaluation of Design Options for the Trace Cache Fetch Mechanism.
193-204
Electronic Edition (IEEE Computer Society DL) BibTeX
Multiprocessing
- Mark Heinrich, Vijayaraghavan Soundararajan, John L. Hennessy, Anoop Gupta:
A Quantitative Analysis of the Performance and Scalability of Distributed Shared Memory.
205-217
Electronic Edition (IEEE Computer Society DL) BibTeX
- Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve:
The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors.
218-226
Electronic Edition (IEEE Computer Society DL) BibTeX
- Seungjoon Park, David L. Dill:
An Executable Specification and Verifier for Relaxed Memory Order.
227-235
Electronic Edition (IEEE Computer Society DL) BibTeX
- Donglai Dai, Dhabaleswar K. Panda:
Exploiting the Benefits of Multiple-Path Network DSM Systems: Architectural Alternatives and Performance Evaluation.
236-244
Electronic Edition (IEEE Computer Society DL) BibTeX
- Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim:
Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors.
245-255
Electronic Edition (IEEE Computer Society DL) BibTeX
- Zheng Zhang, Marcelo H. Cintra, Josep Torrellas:
Excel-NUMA: Toward Programmability, Simplicity, and High Performance.
256-264
Electronic Edition (IEEE Computer Society DL) BibTeX
Volume 48,
Number 3,
March 1999
Interconnection Networks
Cellular Automata
Logic Design
Diagnosis and Testing
Brief Contributions
Volume 48,
Number 4,
April 1999
Graph Partitioning
Fault Tolerance
Hardware/Software Design of Embedded Systems
Diagnosis and Testing
Brief Contributions
Volume 48,
Number 5,
May 1999
Processor Architecture
Fault Tolerance and Diagnosis
Memory Hierarchies for Shared-Memory Multiprocessors
Satisfiability
Brief Contributions
Volume 48,
Number 6,
June 1999
Special Section on Configurable Computing
- Eduardo Sanchez, Moshe Sipper, Jacques-Olivier Haenni, Jean-Luc Beuchat, André Stauffer, Andrés Pérez-Uribe:
Static and Dynamic Configurable Systems.
556-564 BibTeX
- Douglas Chang, Malgorzata Marek-Sadowska:
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs.
565-578 BibTeX
- Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers.
579-590 BibTeX
- Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook:
Dynamic Reconfiguration to Support Concurrent Applications.
591-602 BibTeX
- Hoon Choi, Jong-Sun Kim, Chi-Won Yoon, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung:
Synthesis of Application Specific Instructions for Embedded DSP Software.
603-614 BibTeX
- Claude Thibeault, Guy Bégin:
A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations.
615-627 BibTeX
- Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi:
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing.
628-639 BibTeX
Brief Contributions
Volume 48,
Number 7,
July 1999
Interconnection Networks
Parallel Computation
Algorithms for Systolic Arrays
Fault Tolerance
Brief Contributions
Volume 48,
Number 8,
August 1999
Logic Synthesis
Systems Architecture
Error Correcting Code
Fault Tolerance
Computer Arithmetik
Brief Contributions
Volume 48,
Number 9,
September 1999
Special Section on Multithreaded Architecture
ATM Networks
Testing
Parallel Processing
Logic Synthesis
Verification
Brief Contributions
Volume 48,
Number 10,
October 1999
Cache Memory Systems
Cryptography
Real-Time Systems
Fault Tolerance
Networks
Computer Arithmetic
FPGA Architecture
Brief Contributions
Volume 48,
Number 11,
November 1999
Testing
System Performance
Dependability of Computing Systems
Scheduling in Multiprocessors
Interconnection Network Routing
Networks
Cache Memory Systems
Processor Architecture
Fault Tolerance
Volume 48,
Number 12,
1999
Routing
Testability
Computer Arithmetic
Architecture
Brief Contributions
Copyright © Sun May 17 00:23:04 2009
by Michael Ley (ley@uni-trier.de)
