DATE 2000:
Paris,
France
2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France.
IEEE Computer Society 2000, ISBN 0-7695-0537-6 BibTeX
@proceedings{DBLP:conf/date/2000,
title = {2000 Design, Automation and Test in Europe (DATE 2000), 27-30
March 2000, Paris, France},
booktitle = {DATE},
publisher = {IEEE Computer Society},
year = {2000},
isbn = {0-7695-0537-6},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Embedded Software Generation
Low-Power Issues in System-Level Design
- Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, Giovanni De Micheli, Luca Benini:
Quantitative Comparison of Power Management Algorithms.
20-26
Electronic Edition (link) BibTeX
- Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno:
Efficient Power Co-Estimation Techniques for System-on-Chip Design.
27-34
Electronic Edition (link) BibTeX
- Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
A Discrete-Time Battery Model for High-Level Power Estimation.
35-
Electronic Edition (link) BibTeX
Circuit Analysis and Synthesis
Embedded Tutorial - Design Practices for Better Reliability and Yield
Embedded Tutorial - System Level Design Using C++
IP and Design Reuse
Layout
Heterogeneous Aspects in SOC Testing
System Specification
Implementation of Telecom Systems
Logic Synthesis:
Combination
BIST for Mixed-Signal Applications
Decision Diagram Based Methods
Multi-Processor Architectures and Design Methods
Logic Synthesis:
Performance Optimization
TPG and Diagnosis in BIST
Architectural-Level Synthesis
Analysis of Communication Circuits
- Alper Demir, Peter Feldmann:
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits.
340-344
Electronic Edition (link) BibTeX
- Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney:
A New Approach for Computation of Timing Jitter in Phase Locked Loops.
345-349
Electronic Edition (link) BibTeX
- Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens:
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits.
350-
Electronic Edition (link) BibTeX
Logic Synthesis:
Covering and PTL Circuits
Delay and Functional Testing
Co-Synthesis of Embedded Systems
Hot Topic
Wire Performance
Analogue Aspects of System Testing
Abstraction Techniques
Panel Session - A Design Automation Roadmap for Europe
Interconnect Modelling and Analysis
Mixed A/D System Design
Scheduling and Timing Analysis for Real-Time Embedded Systems
Hot Topic
Dependability Issues in Advanced ICs and Systems
High-Level Power Optimization
Panel Session
Embedded Tutorial
Defect Oriented Test
Simulation and Emulation
- Dragos Lungeanu, C.-J. Richard Shi:
Parallel and Distributed VHDL Simulation.
658-662
Electronic Edition (link) BibTeX
- Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi:
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor.
663-668
Electronic Edition (link) BibTeX
- Stefan Pees, Andreas Hoffmann, Heinrich Meyr:
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language.
669-673
Electronic Edition (link) BibTeX
- Peter M. Maurer:
Logic Simulation Using Networks of State Machines.
674-678
Electronic Edition (link) BibTeX
- Norbert Fröhlich, Volker Gloeckel, Josef Fleischmann:
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level.
679-
Electronic Edition (link) BibTeX
Embedded System Design Frameworks
Power and Cost Issues in Testing
Poster Papers
- Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli:
Dynamic Power Management of Laptop Hard Disk.
736
Electronic Edition (link) BibTeX
- Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel:
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints.
737
Electronic Edition (link) BibTeX
- Christian Paulus, Ulrich Kleine, Roland Thewes:
Area Optimization of Analog Circuits Considering Matching Constraints.
738
Electronic Edition (link) BibTeX
- F. M. Pérez-Montes, F. Medeiro, Rafael Domínguez-Castro, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool.
739
Electronic Edition (link) BibTeX
- Ulf Pillkahn:
Evaluation of Interconnects with TDR.
740
Electronic Edition (link) BibTeX
- Peter Bach, Michael Bosch:
Structural Testing on Real Boards.
741
Electronic Edition (link) BibTeX
- Lovic Gauthier, Ahmed Amine Jerraya:
Cycle-True Simulation of the ST10 Microcontroller.
742
Electronic Edition (link) BibTeX
- Adam Morawiec, Raimund Ubar, Jaan Raik:
Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams.
743
Electronic Edition (link) BibTeX
- José Machado da Silva, J. Soeiro Duarte, José Silva Matos:
Mixed-Signal BIST Using Correlation and Reconfigurable Hardware.
744
Electronic Edition (link) BibTeX
- Karem A. Sakallah, Fadi A. Aloul, João P. Marques Silva:
An Experimental Study of Satisfiability Search Heuristics.
745
Electronic Edition (link) BibTeX
- Sunho Chang, Jong-Sun Kim, Lee-Sup Kim:
A Memory Architecture with 4-Address Configurations for Video Signal Processing.
746
Electronic Edition (link) BibTeX
- Gunter Haug, Udo Kebschull, Wolfgang Rosenstiel:
A Hardware Platform for VLIW Based Emulation of Digital Designs.
747
Electronic Edition (link) BibTeX
- Ashok Halambi, Radu Cornea, Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
Architecture Exploration of Parameterizable EPIC SOC Architectures.
748
Electronic Edition (link) BibTeX
- Sriram Govindarajan, Ranga Vemuri:
Improving the Schedule Quality of Static-List Time-Constrained Scheduling.
749
Electronic Edition (link) BibTeX
- Congguang Yang, Maciej J. Ciesielski:
Synthesis for Mixed CMOS/PTl Logic.
750
Electronic Edition (link) BibTeX
- Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio:
TOP: An Algorithm for Three-Level Optimization of PLDs.
751
Electronic Edition (link) BibTeX
- Janusz Sosnowski, Tomasz Bech:
Testing Arithmetic Coprocessor in System Environment.
752
Electronic Edition (link) BibTeX
- José Manuel Moya, Francisco Moya, Juan Carlos López, Santiago Domínguez:
A Flexible Specification Framework for Hardware-Software Codesign.
753
Electronic Edition (link) BibTeX
- Jingyan Zuo, Stephen W. Director:
An Integrated Design Environment for Early Stage Conceptual Design.
754
Electronic Edition (link) BibTeX
- Hilary J. Kahn, Andy Carpenter, Nigel A. Whitaker:
A Web-Based System for Assessing and Searching for Designs.
755
Electronic Edition (link) BibTeX
- Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos:
A Versatile Built-In Self-Test Scheme for Delay Fault Testing.
756
Electronic Edition (link) BibTeX
- Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian:
Effective Low Power BIST for Datapaths.
757
Electronic Edition (link) BibTeX
- Dirk W. Hoffmann, Thomas Kropf:
Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits.
758
Electronic Edition (link) BibTeX
- Jens Schönherr, Bernd Straube:
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level.
759
Electronic Edition (link) BibTeX
- Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, J. Sosa:
A Single Phase Latch for High Speed GaAs Domino Circuits.
760
Electronic Edition (link) BibTeX
- Alex Niemegeers, Gjalt G. de Jong:
An Incremental Specification Flow for Real Time Embedded Systems.
761
Electronic Edition (link) BibTeX
- Valery A. Vardanian, Liana B. Mirzoyan:
Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check.
762
Electronic Edition (link) BibTeX
- Cecilia Metra, Michele Favalli, Bruno Riccò:
On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values.
763
Electronic Edition (link) BibTeX
- Carsten Wegener, Michael Peter Kennedy:
Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICs.
765
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:05:45 2009
by Michael Ley (ley@uni-trier.de)
