29. DAC 1992:
Anaheim,
California,
USA
Proceedings of the 29th Design Automation Conference,
Anaheim,
California,
USA,
June 8-12,
1992. IEEE Computer Society Press,
1992,
ISBN 0-8186-2822-7
Electrical Analysis
Test Generation
Two Level Logic Synthesis
Tutorial
Partitioning and Floorplanning
Interconnect Simulation
Scheduling and Allocation
Panel
Concurrent Engineering
New Approaches to Placement
Deley-Fault Testing
Synthesis Systems and Representations
Panel
Asymptotic Waveform Evaluation
System-Level Synthesis
Performance Issues in Logic Synthesis
Panel
High-Level Test Generation
Allocation and Binding
Panel
Tutorial
Design Verification and Compaction
Fault Simulation and Fault Diagnosis
- Dong-Ho Lee, Sudhakar M. Reddy:
On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits.
327-331
Electronic Edition (link) BibTeX
- Soumitra Bose, Prathima Agrawal:
Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers.
332-335
Electronic Edition (link) BibTeX
- Hyung Ki Lee, Dong Sam Ha:
HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits.
336-340
Electronic Edition (link) BibTeX
- Amitava Majumdar, Sarma Sastry:
On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits.
341-346
Electronic Edition (link) BibTeX
- Ken Kubiak, Steven Parkes, W. Kent Fuchs, Resve A. Saleh:
Exact Evaluation of Diagnostic Test Resolution.
347-352
Electronic Edition (link) BibTeX
- Sreejit Chakravarty, Minsheng Liu:
Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults.
353-356
Electronic Edition (link) BibTeX
- Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A Novel Approach to Delay-Fault Diagnosis.
357-360
Electronic Edition (link) BibTeX
FPGA Synthesis
Tutorial
Timing Optimization and Verification
Discrete Simulation
Multi-Level Logic Synthesis
Panel
DA for High-Speed Packaging
- Albert E. Ruehli, Hansruedi Heeb:
Challenges and Advances in Electrical Interconnect Analysis.
460-465
Electronic Edition (link) BibTeX
- Paul D. Franzon, Slobodan Simovich, Michael Steer, Mark Basel, Sharad Mehrotra, Tom Mills:
Tools to Aid in Wiring Rule Generation for High Speed Interconnects.
466-471
Electronic Edition (link) BibTeX
- Norman H. Chang, Keh-Jeng Chang, John Leo, Ken Lee, Soo-Young Oh:
IPDA: Interconnect Performance Design Assistant.
472-477
Electronic Edition (link) BibTeX
Technology Mapping in Logic Synthesis
Panel
Frameworks
- Margarida F. Jacome, Stephen W. Director:
Design Process Management for CAD Frameworks.
500-505
Electronic Edition (link) BibTeX
- Robert Beggs, John Sawaya, Catharine Ciric, Julius Etzl:
Automated Design Decision Support System.
506-511
Electronic Edition (link) BibTeX
- Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain:
Application-Driven Design Automation for Microprocessor Design.
512-517
Electronic Edition (ACM DL) BibTeX
Global Issues in Routing
Path Delay Analysis
Sequential Logic Synthesis
Panel
Multi-Layer Channel and Over-the-Cell Routing
- Sung-Chuan Fang, Wu-Shiung Feng, Shian-Lang Lee:
A New Efficient Approach to Multilayer Channel Routing Problem.
579-584
Electronic Edition (link) BibTeX
- Takashi Fujii, Yoko Mima, Tsuneo Matsuda, Takeshi Yoshimura:
A Multi-Layer Channel Router with New Style of Over-the-Cell Routing.
585-588
Electronic Edition (link) BibTeX
- Tai-Tsung Ho:
New Models for Four- and Five-Layer Channel Routing.
589-593
Electronic Edition (link) BibTeX
- Cliff Yungchin Hou, C. Y. Roger Chen:
A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing.
594-599
Electronic Edition (link) BibTeX
- Sivakumar Natarajan, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh:
Over-the-Cell Channel Routing for High Performance Circuits.
600-603
Electronic Edition (link) BibTeX
- Bo Wu, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh:
Over-the-Cell Routers for New Cell Model.
604-607
Electronic Edition (link) BibTeX
Automated Approaches to Formal Verification of Hardware
- Yung-Te Lai, Sarma Sastry:
Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification.
608-613
Electronic Edition (link) BibTeX
- Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda:
A New Model for Improving symbolic Product Machine Traversal.
614-619
Electronic Edition (link) BibTeX
- Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel:
Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams.
620-623
Electronic Edition (link) BibTeX
- M. Ray Mercer, Rohit Kapur, Don E. Ross:
Functional Approaches to Generating Orderings for Efficient Symbolic Representations.
624-627
Electronic Edition (link) BibTeX
- June-Kyung Rho, Fabio Somenzi:
Inductive Verification of Iterative Systems.
628-633
Electronic Edition (link) BibTeX
- Yew-Hong Leong, William P. Birmingham:
The Automatic Generation of Bus-Interface Models.
634-637
Electronic Edition (link) BibTeX
Advances in High-Level Synthesis
Tutorial - EDIF/CFI - A User's Perspective
Routing for Special Applications
Issues in Analog CAD
Panels
Copyright © Sat May 16 23:04:36 2009
by Michael Ley (ley@uni-trier.de)
